AD8600 Datasheet, PDF (1/16 Pages) Analog Devices – 16-Channel, 8-Bit Multiplying DAC

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FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
16-Channel, 8-Bit
Multiplying DAC
AD8600*
FUNCTIONAL BLOCK DIAGRAM
R/W RS VDD1 LD VDD2
V_REF V_CC
CS
CONTROL
EN
LOGIC
O0
O1
O2
A3
O3
A2
ADDRESS
O4
A1
DECODE
O5
A0
16 x 8
16
O6
DAC
8-BIT
O7
DB7
REGISTERS
DACS
O8
DB6
O9
DB5
16 x 8
O10
DB4
INPUT
O11
DB3
REGISTERS
O12
DB2
O13
DB1
AD8600
O14
DB0
O15
D_GND1
D_GND2 DACGND V_EE
GENERAL DESCRIPTION
The AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to V_REF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below V_CC. Changes in
reference voltage values and digital inputs will settle within
± 1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
*Patent pending.
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
R/W•CS•ADDR•EN V_DD1
V_DD2 LD•EN V_REF
V_CC
DB7...DB0
INPUT
DAC
R-2R
REGISTER
REGISTER
DAC
O_X
RS
D_GND2 RS DACGND
V_EE
D_GND1
R/W•CS•ADDRESS
Figure 1. Equivalent DAC Channel
REV. 0
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use, nor for any infringements of patents or other rights of third parties
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