AD8339_15 Datasheet, PDF (1/36 Pages) Analog Devices – DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter

Data Sheet
DC to 50 MHz, Quad I/Q Demodulator
and Phase Shifter
AD8339
FEATURES
Quad integrated I/Q demodulator
16 phase select on each output (22.5° per step)
Quadrature demodulation accuracy
Phase accuracy: ±1°
Amplitude imbalance: ±0.05 dB
Bandwidth
4LO: LF to 200 MHz
RF: LF to 50 MHz
Baseband: determined by external filtering
Output dynamic range: 160 dB/Hz
LO drive: >0 dBm (50 Ω), single-ended sine wave
Supply: ±5 V
Power consumption: 73 mW/channel (290 mW total)
Power-down via SPI (each channel and complete chip)
APPLICATIONS
Medical imaging (CW ultrasound beamforming)
Phased array systems
Radar
Adaptive antennas
Communication receivers
GENERAL DESCRIPTION
The AD8339¹ is a quad I/Q demodulator configured to be
driven by a low noise preamplifier with differential outputs. It is
optimized for the LNA in the AD8332/AD8334/AD8335 family
of VGAs. The part consists of four identical I/Q demodulators
with a 4× local oscillator (LO) input that divides the signal and
generates the necessary 0° and 90° phases of the internal LO
that drive the mixers. The four I/Q demodulators can be used
independently of each other (assuming that a common LO is
acceptable) because each has a separate RF input.
Continuous wave (CW) analog beamforming (ABF) and I/Q
demodulation are combined in a single 40-lead, ultracompact
chip scale device, making the AD8339 particularly applicable in
high density ultrasound scanners. In an ABF system, time
domain coherency is achieved following the appropriate phase
alignment and summation of multiple receiver channels. A reset
pin synchronizes multiple ICs to start each LO divider in the
same quadrant. Sixteen programmable 22.5° phase increments
are available for each channel. For example, if Channel 1 is used
as a reference and Channel 2 has an I/Q phase lead of 45°, the
user can phase align Channel 2 with Channel 1 by choosing the
appropriate phase select code.
1 _{Protected by U.S. Patent Number 7,760,833.}
Rev. B
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FUNCTIONAL BLOCK DIAGRAM
RF1N RF1P
AD8339
RSTS
SCLK
SDI
SDO
CSB
RF2P
RF2N
4LOP
4LON
RF3P
RF3N
VPOS
VNEG
SERIAL
INTERFACE
0°
÷4 _90°
BIAS
Φ
I1OP
Φ
Q1OP
Φ
I2OP
Φ
Q2OP
Φ
I3OP
Φ
Q3OP
Φ
I4OP
Φ
Q4OP
RF4N RF4P
Figure 1.
The mixer outputs are in current form for convenient summa-
tion. The independent I and Q mixer output currents are summed
and converted to a voltage by a low noise, high dynamic range,
current-to-voltage (I-V) transimpedance amplifier, such as the
AD8021 or the AD829. Following the current summation, the
combined signal is applied to a high resolution analog-to-digital
converter (ADC), such as the AD7665 (16-bit, 570 kSPS).
An SPI-compatible serial interface port is provided to easily
program the phase of each channel; the interface allows daisy
chaining by shifting the data through each chip from SDI to SDO.
The SPI also allows for power-down of each individual channel
and the complete chip. During power-down, the serial interface
remains active so that the device can be programmed again.
The dynamic range is typically 160 dB/Hz at the I and Q
outputs. The AD8339 is available in a 6 mm × 6 mm, 40-lead
LFCSP and is specified over the industrial temperature range of
−40°C to +85°C.
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