AD8326 Datasheet, PDF (1/24 Pages) Analog Devices – High Output Power Programmable CATV Line Driver

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High Output Power
Programmable CATV Line Driver
AD8326
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 0.75 dB Steps over a 53.5 dB Range
Low Distortion at 65 dBmV Output
–62 dBc SFDR at 21 MHz
–58 dBc SFDR at 65 MHz
1 dB Compression of 25 dBm at 10 MHz
Output Noise Level
–45 dBmV in 160 kHz
Maintains 75 ⍀ Output Impedance
Power-Up and Power-Down Condition
Upper Bandwidth: 100 MHz (Full Gain Range)
Single or Dual Supply Operation
APPLICATIONS
Gain-Programmable Line Driver
CATV Telephony Modems
CATV Terminal Devices
General-Purpose Digitally Controlled Variable Gain Block
GENERAL DESCRIPTION
The AD8326 is a high-output power, digitally controlled, vari-
able gain amplifier optimized for coaxial line driving applications
such as data and telephony cable modems that are designed to
the MCNS-DOCSIS upstream standard. An 8-bit serial word
determines the desired output gain over a 53.5 dB range result-
ing in gain changes of 0.75 dB/LSB. The AD8326 is offered in
two models, each optimized to support the desired output power
and resulting performance.
The AD8326 comprises a digitally controlled variable attenuator
of 0 dB to –54 dB, that is preceded by a low noise, fixed-gain
buffer and is followed by a low distortion high-power amplifier.
The AD8326 accepts a differential or single-ended input signal.
The output is designed to drive a 75 Ω load, such as coaxial
cable, although the AD8326 is capable of driving other loads.
When driving 67 dBm into a 75 Ω load, the AD8326ARP
provides a worst harmonic of only –59 dBc at 21 MHz and
–57 dBc at 42 MHz. When driving 65 dBmV into a 75 Ω load,
the AD8326ARE provides a worst harmonic of only –62 dBc at
21 MHz and –60 dBc at 42 MHz.
FUNCTIONAL BLOCK DIAGRAM
V_CC (7 PINS)
BYP
AD8326
V_IN+
V_IN–
DIFF OR
SINGLE
INPUT
AMP
VERNIER
Z_IN (SINGLE) = 800⍀
Z_IN (DIFF) = 1.6k⍀
ATTENUATION
CORE
8
DECODE
POWER
AMP
Z_OUT DIFF =
75⍀
V_OUT+
V_OUT–
8
DATA LATCH
POWER-DOWN
LOGIC
8
SHIFT
REGISTER
GND
DATEN DATA CLK V_EE (10 PINS) TXEN SLEEP
–40
ARP(V_S = +12V)
ARE(V_S = ؎5V)
–45
–50
ARP(V_O = 69dBmV)
–55
ARP(V_O = 67dBmV)
–60
–65 ^{ARE(VO = 65dBmV)}
–70
ARE(V_O = 62dBmV)
–75
–80
5
15
25
35
45
55
65
FREQUENCY – MHz
Figure 1. Worst Harmonic Distortion vs. Frequency
The differential output of the AD8326 is compliant with DOCSIS
paragraph 4.2.10.2 for “Spurious Emissions During Burst On/Off
Transients.” In addition, this device has a sleep mode function
that reduces the quiescent current to 4 mA.
The AD8326 is packaged in a low-cost 28-lead TSSOP and a
28-lead P (power) SOIC. Both devices have an operational tem-
perature range of –40°C to +85°C.
REV. 0
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© Analog Devices, Inc., 2001