AD8309 Datasheet, PDF (1/20 Pages) Analog Devices – 5 MHz.500 MHz 100 dB Demodulating Logarithmic Amplifier with Limiter Output

a 5 MHz–500 MHz 100 dB Demodulating
Logarithmic Amplifier with Limiter Output
AD8309
FEATURES
Complete Multistage Log-Limiting IF Amplifier
100 dB Dynamic Range: –78 dBm to +22 dBm (Re 50 ⍀)
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
؎0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 100 dB, Bandwidth 500 MHz
Constant Phase (Typical ؎80 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, R_IN = 1 k⍀, C_IN = 2.5 pF
500 ns Power-Up Time, <1 ␮A Sleep Current
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
FUNCTIONAL BLOCK DIAGRAM
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
INHI
INLO
12dB
LADR ATTEN
4 ؋ DET
DET
12dB
DET
12dB
LIM
DET
BIAS
CTRL
LMHI
LMLO
LMDR
TEN DETECTORS SPACED 12dB
I-V
VLOG
FLTR
ENBL
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
BIAS
INTERCEPT
TEMP COMP
PRODUCT DESCRIPTION
The AD8309 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 500 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and
typically 2 mA, providing a limiter gain of 100 dB when using
200 Ω loads. A CMOS-compatible control interface can enable
the AD8309 within about 500 ns and disable it to a standby
current of under 1 µA.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (×4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 kΩ in
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50 Ω, source is 1.28 nV/√Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8309 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50 Ω level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each
of 2 V in amplitude, which would correspond to a sine wave
power of +22 dBm if the differential input were terminated in
50 Ω. The slope of the RSSI output is closely controlled to
20 mV/dB, while the intercept is set to –108 dBV (–95 dBm
re 50 Ω). These scaling parameters are determined by a band-
gap voltage reference and are substantially independent of tem-
perature and supply. The logarithmic law conformance is typically
within ± 0.4 dB over the central 80 dB of this range at any fre-
quency between 10 MHz and 200 MHz, and is degraded only
slightly at 500 MHz.
The RSSI response time is nominally 67 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50 Ω and
this interface remains stable with any value of capacitance on
the output.
The AD8309 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead TSSOP package.
REV. B
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© Analog Devices, Inc., 1999