AD8195ACPZ Datasheet, PDF (1/20 Pages) Analog Devices – HDMI/DVI Buffer with Equalization

Data Sheet
HDMI/DVI Buffer with Equalization
AD8195
FEATURES
1 input, 1 output HDMI/DVI link
Enables HDMI 1.3a-compliant front panel input
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 m at 2.25 Gbps)
Preemphasized outputs
Fully buffered unidirectional inputs/outputs
50 Ω on-chip terminations
Low added jitter
Transmitter disable feature
Reduces power dissipation
Disables input termination
3 auxiliary buffered channels per link
Bidirectional buffered DDC lines (SDA and SCL)
Bidirectional buffered CEC line with integrated pull-up
resistors (27 kΩ)
Independently powered from 5 V of HDMI input
connector
Logic level translation (3.3 V, 5 V)
Input/output capacitance isolation
Standards compatible: HDMI, DVI, HDCP, DDC, CEC
40-lead LFCSP_VQ package (6 mm × 6 mm)
APPLICATIONS
Front panel buffer for advanced television (HDTV) sets
GENERAL DESCRIPTION
The AD8195 is an HDMI/DVI buffer featuring equalized TMDS
inputs and preemphasized TMDS outputs, ideal for systems with
long cable runs. The AD8195 includes bidirectional buffering
for the DDC bus and bidirectional buffering with integrated
pull-up resistors for the CEC bus. The DDC and CEC buffers
are powered independently of the TMDS buffers so that DDC/
CEC functionality can be maintained when the system is powered
off. The AD8195 meets all the requirements for sink tests as
defined in Section 8 of the HDMI Compliance Test 1.3c.
The AD8195 is specified to operate over the −40°C to +85°C
temperature range.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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FUNCTIONAL BLOCK DIAGRAM
PARALLEL
VTTI
CONTROL
LOGIC
AD8195
AVCC
AMUXVCC
AVEE
VTTO
IP[3:0] ⁺
IN[3:0] ^–
VREF_IN
4
4
4
EQ
BUFFER
PE ⁴
HIGH SPEED BUFFERED
+ _OP[3:0]
– _ON[3:0]
VREF_OUT
SCL_IN
SDA_IN
2
2
SCL_OUT
SDA_OUT
CEC_IN
LOW SPEED BUFFERED
BIDIRECTIONAL
Figure 1.
CEC_OUT
TYPICAL APPLICATION
MEDIA CENTER
SET-TOP BOX
DVD PLAYER
HDMI
RECEIVER
4:1 HDMI
SWITCH
HDTV SET
AD8195
GAME
CONSOLE
BACK PANEL
CONNECTORS
FRONT PANEL
CONNECTOR
Figure 2. Typical AD8195 Application for HDTV Sets
PRODUCT HIGHLIGHTS
1. Enables a fully HDMI 1.3a-compliant front panel input.
2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
3. Input cable equalizer enables use of long cables; more than
20 meters (24 AWG) at data rates of up to 2.25 Gbps.
4. Auxiliary buffer isolates and buffers the DDC bus and CEC
line for a single chip, fully HDMI 1.3a-compliant solution.
5. Auxiliary buffer is powered independently from the TMDS
link so that DDC/CEC functionality can be maintained
when the system is powered off.
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