AD8117 Datasheet, PDF (1/32 Pages) Analog Devices – Video Crosspoint Switch Video Crosspoint Switch

Preliminary Technical Data
FEATURES
Large, 32 x 32 High Speed, Nonblocking Switch Array
G = 1 (AD8117) or G = 2 (AD8118) Operation
Differential or Single-Ended Operation
Single +5 V supply, or dual ± 2.5 V supply
Serial or Parallel Programming of Switch Array
High impedance output disable allows connection of
multiple devices with minimal output bus load
Excellent Video Performance
100 MHz 0.1 dB Gain Flatness
0.1% Differential Gain Error (RL = 150 Ω)
0.1° Differential Phase Error (RL = 150 Ω)
Excellent AC Performance
Bandwidth: >500 MHz
Slew rate: 1,800 V/µs
Low power of 2.5 W
Low all hostile crosstalk:
-75 dB @ 5 MHz
-40 dB @ 500 MHz
Reset pin allows disabling of all outputs
(Connected through a capacitor to ground provides
power-on reset capability)
304 ball SBGA package (31 mm × 31 mm)
APPLICATIONS
Routing of high speed signals including:
RGB and component video routing
Compressed video (MPEG, Wavelet)
Data communications
PRODUCT DESCRIPTION
The AD8117/AD8118 is a high speed 32 × 32 video crosspoint
switch matrix. It offers a 500 MHz bandwidth and slew rate of
1800 V/µs for high resolution computer graphics (RGB) signal
switching. With −75 dB of crosstalk and −100 dB isolation (@
5 MHz), the AD8117 is useful in many high-speed applications.
The 0.1 dB flatness out to 100 MHz makes the AD8117 ideal for
composite video switching.
The AD8117's 32 independent output buffers can be placed into
a high impedance state for paralleling crosspoint outputs so that
off-channels present minimal loading to an output bus. The
AD8117 is available in gain of 1 or 2 (AD8118) for ease of use in
Rev. PrA
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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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500 MHz, 32 x 32 Buffered
Video Crosspoint Switch
AD8117/AD8118
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4 D5
VDD DGND
WE
CLK
DATA IN
UPDATE
RESET
1
0
AD8117
(AD8118)
192-BIT SHIFT REGISTER
WITH 6-BIT
PARALLEL LOADING
192
PARALLEL LATCH
192
32
x
DECODE
6:32 DECODERS
32
INPUT
RECEIVER
G = +1
(G = +2)
2
OUTPUT
1024 ^BUFFER
G = +1
A0
A1
A2
A3
A4
DATA
OUT
2
32 INPUT
PAIRS
SWITCH
MATRIX
32
OUTPUT
PAIRS
VPOS VNEG
VOCM
Figure 1. AD8117 G = +1
back-terminated load applications. It operates as a fully
differential device or can be configured for single-ended
operation. Either a single +5 V supply, or dual ± 2.5 V supplies
can be used while consuming only 500 mA of idle current with
all outputs enabled. The channel switching is performed via a
double-buffered, serial digital control (which can accommodate
daisy chaining of several devices) or via a parallel control
allowing updating of an individual output without
reprogramming the entire array.
The AD8117/AD8118 is packaged in a 304 Ball BGA package
and is available over the extended industrial temperature range
of −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
www.analog.com
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.