AD7920_15 Datasheet, PDF (1/24 Pages) Analog Devices – 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70

250 kSPS,
10-/12-Bit ADCs in 6-Lead SC70
AD7910/AD7920
FEATURES
Throughput rate: 250 kSPS
Specified for VDD of 2.35 V to 5.25 V
Low power
3.6 mW typ at 250 kSPS with 3 V supplies
12.5 mW typ at 250 kSPS with 5 V supplies
Wide input bandwidth
71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA max
6-lead SC70 package
8-lead MSOP package
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The AD7910/AD7920¹ are, respectively, 10-bit and 12-bit, high
speed, low power, successive approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is initiated at this
point. There are no pipeline delays associated with the part.
The AD7910/AD7920 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
Rev. C
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FUNCTIONAL BLOCK DIAGRAM
V_DD
V_IN
T/H
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7910/AD7920
GND
Figure 1.
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. 10-/12-bit ADCs in SC70 and MSOP packages.
2. Low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when power-down mode is used while not
converting. The part also features a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 μA maximum and 50 nA typically
when in power-down mode.
4. Reference derived from the power supply.
5. No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
1 _{Protected by U.S. Patent No. 6,681,332.}
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