AD7781 Datasheet, PDF (1/16 Pages) Analog Devices – 20-Bit, Pin-Programmable, Low Power Sigma-Delta ADC

FEATURES
Pin-programmable filter response
Update rate: 10 Hz or 16.7 Hz
Pin-programmable in-amp gain
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Internal bridge power-down switch
Current
115 μA typical (gain = 1)
330 μA typical (gain = 128)
Simultaneous 50 Hz/60 Hz rejection
Power supply: 2.7 V to 5.25 V
−40°C to +105°C temperature range
Independent interface power supply
Packages
14-lead, narrow body SOIC
16-lead TSSOP
2-wire serial interface (read-only device)
SPI compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Pressure measurement
Industrial process control
Portable instrumentation
GENERAL DESCRIPTION
The AD7781 is a complete, low power front-end solution for
bridge sensor products, including weigh scales, strain gages,
and pressure sensors. It contains a precision, low power, 20-bit
sigma-delta (Σ-Δ) ADC, an on-chip, low noise programmable
gain amplifier (PGA), and an on-chip oscillator.
Consuming only 330 μA, the AD7781 is particularly suitable for
portable or battery-operated products where very low power is
required. The AD7781 also has a power-down mode that allows
the user to switch off the power to the bridge sensor and power
down the AD7781 when not converting, thus increasing the
battery life of the product.
For ease of use, all the features of the AD7781 are controlled by
dedicated pins. Each time that a data read occurs, eight status bits
are appended to the 20-bit conversion. These status bits contain a
pattern sequence that can be used to confirm the validity of the
serial transfer.
Rev. 0
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20-Bit, Pin-Programmable,
Low Power Sigma-Delta ADC
AD7781
FUNCTIONAL BLOCK DIAGRAM
GND ^AVDD GAIN
REFIN(+) REFIN(–)
AIN(+)
AIN(–)
G=1
OR 128
20-BIT Σ-Δ
ADC
BPDSW
AD7781
INTERNAL
CLOCK
Figure 1.
DOUT/RDY
SCLK
DV_DD
FILTER
PDRST
Table 1.
Parameter
Output Data Rate
RMS Noise
C Grade
B Grade
P-P Resolution
C Grade
B Grade
Settling Time
Gain = 128
10 Hz 16.7 Hz
44 nV
55 nV
65 nV
90 nV
17.6
17.3
300 ms
17.1
16.6
120 ms
Gain = 1
10 Hz 16.7 Hz
2.4 μV
2.4 μV
2.7 μV
2.7 μV
18.8
18.8
300 ms
18.7
18.7
120 ms
The on-chip PGA has a gain of 1 or 128, supporting a full-scale
differential input of ±5 V or ±39 mV. The device has two filter
response options. The filter response at the 16.7 Hz update rate
provides superior dynamic performance. The settling time is
120 ms at this update rate. At the 10 Hz update rate, the filter
response provides better than −45 dB of stop-band attenuation.
In load cell applications, this stop-band rejection is useful to
reject low frequency mechanical vibrations of the load cell. The
settling time is 300 ms at this update rate. Simultaneous 50 Hz/
60 Hz rejection occurs at both the 10 Hz and 16.7 Hz update rates.
The AD7781 operates with a power supply from 2.7 V to 5.25 V.
It is available in a narrow body, 14-lead SOIC package and in a
16-lead TSSOP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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