AD7616-P Datasheet, PDF (1/47 Pages) Analog Devices – 16-Channel DAS with 16-Bit, Bipolar Input, Dual Simultaneous Sampling ADC

Data Sheet
16-Channel DAS with 16-Bit, Bipolar Input,
Dual Simultaneous Sampling ADC
AD7616-P
FEATURES
16-channel, dual, simultaneously sampled inputs
Independently selectable channel input ranges
True bipolar: ±10 V, ±5 V, ±2.5 V
Single 5 V analog supply and 2.3 V to 3.6 V V_DRIVE supply
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
1st-order antialiasing analog filter
On-chip accurate reference and reference buffer
Dual 16-bit SAR ADC
Throughput rate: 2 × 1 MSPS
Oversampling capability with digital filter
Flexible sequencer with burst mode
Parallel digital interface
Optional CRC error checking
Hardware/software configuration
Performance
92 dB SNR at 500 kSPS (2× OSR)
90.5 dB SNR at 1 MSPS
−103 dB THD
±1 LSB INL (typical), ±0.99 LSB DNL (maximum)
8 kV ESD rating on analog input pins
On-chip self detect function
80-lead LQFP package
APPLICATIONS
Power line monitoring
Protective relays
Multiphase motor control
Instrumentation and control systems
Data acquisition systems (DASs)
GENERAL DESCRIPTION
The AD7616-P is a 16-bit, DAS that supports dual simultaneous
sampling of 16 channels. The AD7616-P operates from a single
5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true
bipolar input signals while sampling at throughput rates up to
1 MSPS per channel pair with 90.5 dB SNR. Higher signal-to-
noise ratio (SNR) performance can be achieved with the on-chip
oversampling mode (92 dB for an oversampling ratio (OSR) of 2).
The input clamp protection circuitry tolerates voltages up to
±21 V. The AD7616-P has 1 MΩ analog input impedance,
regardless of sampling frequency. The single-supply operation,
on-chip filtering, and high input impedance eliminate the need
for driver op amps and external bipolar supplies.
The device contains analog input clamp protection, a dual, 16-bit
charge redistribution successive approximation register (SAR)
analog-to-digital converter (ADC), a flexible digital filter, a
2.5 V reference and reference buffer, and a high speed parallel
interface.
FUNCTIONAL BLOCK DIAGRAM
V_CC
REFCAP REFINOUT REFSEL REGCAP REGCAPD VDRIVE
V0A
V0AGND
CLAMP ^1MΩ
CLAMP
1MΩ
R_FB
R_FB
FIRST-
ORDER LPF
V7A
V7AGND
V0B
V0BGND
V7B
V7BGND
CLAMP ^1MΩ
CLAMP
1MΩ
CLAMP ^1MΩ
CLAMP
1MΩ
CLAMP ^1MΩ
CLAMP
1MΩ
R_FB
R_FB
R_FB
R_FB
R_FB
R_FB
FIRST-
ORDER LPF
FIRST-
ORDER LPF
FIRST-
ORDER LPF
AD7616-P ^VCC
ALDO
2:1
MUX
9:1
MUX
9:1
MUX
2.5V
REF
1.8V
ALDO
1.8V
DLDO
16-BIT
SAR
16-BIT
SAR
OSR
DIGITAL
FILTER
PARALLEL
INTERFACE PARALLEL
PAR
DB15 TO DB0
FLEXIBLE
SEQUENCER
CLK OSC
CONTROL
INPUTS
RESET
WR/BURST
SEQEN
HW_RNGSEL0, HW_RNGSEL1
CHSEL2 TO CHSEL0
BUSY
CONVST
AGND
Figure 1.
DGND
Rev. 0
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