AD7476 Datasheet, PDF (1/20 Pages) Analog Devices – 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23

FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V_DD of 2.35 V to 5.25 V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI^®/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 ␮A Max
6-Lead SOT-23 Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors
1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478^*
FUNCTIONAL BLOCK DIAGRAM
V_DD
V_IN
T/H
8-/10-/12-BIT
SUCCESSIVE-
APPROXIMATION
ADC
CONTROL
LOGIC
AD7476/AD7477/AD7478
GND
SCLK
SDATA
CS
GENERAL DESCRIPTION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, high speed, low power, successive-approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 6 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from V_DD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 V to V_DD. The conversion
rate is determined by the SCLK.
PRODUCT HIGHLIGHTS
1. First 12-/10-/8-Bit ADCs in a SOT-23 Package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The part also features a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 µA maximum
when in shutdown.
4. Reference Derived from the Power Supply.
5. No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
*Protected by U.S.Patent No. 6,681,332.
REV. D
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