AD7457 Datasheet, PDF (1/20 Pages) Analog Devices – Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23

Low Power, Pseudo Differential, 100 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7457
FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power:
0.9 mW max at 100 kSPS with VDD = 3 V
3 mW max at 100 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70-dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface—SPI®/QSPI™/
MICROWIRE™/DSP compatible
Automatic power-down mode
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies in excess of 1 MHz. The reference voltage for the
AD7457 is applied externally to the VREF pin and can range from
100 mV to VDD, depending on what suits the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs.
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7457 uses advanced design techniques to achieve very
low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
V_DD
V_IN+
V_IN–
V_REF
12-BIT
T/H
SUCCESSIVE
APPROXIMATION
ADC
AD7457
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V power supplies.
2. Low power consumption. With a 3 V supply, the AD7457
offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.
3. Pseudo differential analog input.
4. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power-
down after conversion allows the average power
consumption to be reduced.
5. Variable voltage reference input.
6. No pipeline delay.
7. Accurate control of the sampling instance via the CS input
and once-off conversion control.
8. ENOB > 10 bits typically with 500 mV reference.
Rev. 0
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