AD7453BRTZ-REEL7 Datasheet, PDF (1/20 Pages) Analog Devices – Pseudo Differential, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23

FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with VDD = 3 V
7.25 mW max at 555 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7453¹ is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
pseudo differential analog input. This part operates from a
single 2.7 V to 5.25 V power supply and features throughput
rates up to 555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input frequen-
cies up to 3.5 MHz. The reference voltage for the AD7453 is
applied externally to the VREF pin and can range from 100 mV to
VDD, depending on the power supply and what suits the
application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS; the conversion is also initiated at this
point.
The SAR architecture of this part ensures that there are no
pipeline delays. The AD7453 uses advanced design techniques
to achieve very low power dissipation.
Pseudo Differential, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7453
FUNCTIONAL BLOCK DIAGRAM
V_DD
V_IN+
V_IN–
V_REF
12-BIT
T/H
SUCCESSIVE
APPROXIMATION
ADC
AD7453
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V Power Supplies.
2. High Throughput with Low Power Consumption. With a
3 V supply, the AD7453 offers 3.3 mW max power
consumption for a 555 kSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate control of the sampling instant via a CS input and
once-off conversion control.
8. ENOB > 10 bits Typically with 500 mV Reference.
1_{Protected by U.S. Patent Number 6,681,332.}
Rev. B
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