AD73460_15 Datasheet, PDF (1/32 Pages) Analog Devices – Six-Input Channel Analog Front End

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FEATURES
AFE PERFORMANCE
6 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
72 dB SNR
64 kS/s Maximum Sample Rate
–80 dB Crosstalk
Low Group Delay (25 ␮s Typ per ADC Channel)
Programmable Input Gain
Single Supply Operation
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Six-Input Channel
Analog Front End
AD73460
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
AD73460
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
8K)
8K)
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATABUS
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
BYTE DMA
CONTROLLER
ADSP-2100 BASE
ARCHITECTURE
REF
SERIAL PORT
SPORT 2
ADC1 ADC2 ADC3 ADC4 ADC5 ADC6
ANALOG FRONT END
SECTION
GENERAL DESCRIPTION
The AD73460 is a six-input channel analog front end processor
for general-purpose applications including industrial power meter-
ing or multichannel analog inputs. It features six 16-bit A/D
conversion channels, each of which provides 72 dB signal-to-noise
ratio over a dc-to-2 kHz signal bandwidth. Each channel also
features a programmable input gain amplifier (PGA) with gain
settings in eight stages from 0 dB to 38 dB.
The AD73460 is particularly suitable for industrial power metering
since each channel samples synchronously, ensuring that there
is no (phase) delay between the conversions. The AD73460 also
features low group delay conversions on all channels.
An on-chip reference voltage of 1.25 V is included. The sampling
rate of the device is programmable with separate settings
offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of input channels by cas-
cading an extra AFE external to the AD73460.
The AD73460’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The AD73460-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and 16K
(16-bit) of data RAM. The AD73460-40 integrates 40K bytes
of on-chip memory configured as 8K words (24-bit) of program
RAM and 8K (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The AD73460 is available in a 119-ball
PBGA package.
REV. A
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