AD7304 Datasheet, PDF (1/14 Pages) Analog Devices – +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC

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+3 V/+5 V, Rail-to-Rail
Quad, 8-Bit DAC
AD7304/AD7305*
FEATURES
Four 8-Bit DACs in One Package
+3 V, +5 V and ؎5 V Operation
Rail-to-Rail REF-Input to Voltage Output Swing
2.6 MHz Reference Multiplying Bandwidth
Compact 1.1 mm Height TSSOP 16-/20-Lead Package
Internal Power ON Reset
SPI Serial Interface Compatible—AD7304
Fast Parallel Interface—AD7305
40 ␮A Power Shutdown
APPLICATIONS
Automotive Output Span Voltage
Instrumentation, Digitally Controlled Calibration
Pin-Compatible AD7226 Replacement when V_DD < 5.5 V
GENERAL DESCRIPTION
The AD7304/AD7305 are quad, 8-bit DACs that operate from a
single +3 V to +5 V supply or ±5 V supplies. The AD7304 has a
serial interface, while the AD7305 has a parallel interface. Inter-
nal precision buffers swing rail-to-rail. The reference input range
includes both supply rails allowing for positive or negative full-
scale output voltages. Operation is guaranteed over the supply
voltage range of +2.7 V to +5.5 V, consuming less than 9 mW
from a +3 V supply.
The full-scale voltage output is determined by the external refer-
ence input voltage applied. The rail-to-rail V_REF input to DAC
V_OUT allows for a full-scale voltage set equal the positive supply
V_DD, the negative supply V_SS or any value in between.
The AD7304’s doubled-buffered serial-data interface offers high
speed, three-wire, SPI and microcontroller compatible inputs
using data in (SDI), clock (CLK) and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input regis-
ters. The double buffered architecture allows all four input
registers to be preloaded with new values, followed by a LDAC
control strobe which copies all the new data into the DAC regis-
ters thereby updating the analog output values. When operating
from less than +5.5 V, the AD7305 is pin-compatible with the
popular industry standard AD7226.
FUNCTIONAL BLOCK DIAGRAMS
V_DD
V_REFB V_REFA
PWR ON
RESET
8
INPUT ⁸ DAC A ⁸
REG A
REG
INPUT ⁸ DAC B ⁸
REG B
REG
DAC A
DAC B
V_OUTA
V_OUTB
CS
SDI/SHDN
CLK
SERIAL
REG
INPUT ⁸ DAC C ⁸
REG C
REG
INPUT ⁸ DAC D ⁸
REG D
REG
DAC C
DAC D
V_OUTC
V_OUTD
AD7304
DB0
DB1
DB2
DB3
DB4
DB5
DB6
WR
A0/SHDN
A1
V_SS GND
V_DD
CLR LDAC ^VREF^{C V}REF^D
V_REF
PWR ON
RESET
8
INPUT 8 DAC A ⁸
REG A
REG
INPUT ⁸ DAC B ⁸
REG B
REG
INPUT 8 DAC C ⁸
REG C
REG
INPUT 8 DAC D 8
REG D
REG
DAC A
DAC B
DAC C
DAC D
DECODE
AD7305
LDAC
V_SS GND
V_OUTA
V_OUTB
V_OUTC
V_OUTD
An internal power ON reset places both parts in the zero-scale
state at turn ON. A 40 µA power shutdown (SHDN) feature is
activated on both parts by tristating the SDI/SHDN pin on the
AD7304, and tristating the A0/SHDN address pin on the
AD7305.
The AD7304/AD7305 are specified over the extended industrial
(–40°C to +85°C), and the automotive (–40°C to +125°C)
temperature ranges. AD7304s are available in 16-lead plastic
DIP (N-16), and wide-body SOL-16 (R-16) packages. The
parallel input AD7305 is available in the 20-lead plastic DIP
(N-20), and the SOL-20 (R-20) surface mount package. For
ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16)
package will be available for the AD7304, while the TSSOP-20
(RU-20) will house the AD7305.
*Protected under Patent Number 5684481.
REV. A
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© Analog Devices, Inc., 1998