AD7266 Datasheet, PDF (1/17 Pages) Analog Devices – Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC

Preliminary Technical Data
FEATURES
Dual 12-bit, 3-channel ADC
Fast throughput rate: 2 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power: 12 mW max at 1.5 MSPS with 3 V supplies
30 mW max at 2 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
–40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages
GENERAL DESCRIPTION
The AD7266¹ is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
sors or DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7266 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
2 MSPS throughput rate, the part consumes 4 mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V to
VREF range or a 2VREF range with either straight binary or twos
complement output coding. The AD7266 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7266 is available in 32-lead lead frame chip scale (LFCSP) and
thin quad flat (TQFP) packages.
1_{Protected by U.S. Patent No. 6,681,332.}
Rev. PrG
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Differential Input, Dual 2 MSPS,
12-Bit, 3-Channel SAR ADC
AD7266
FUNCTIONAL BLOCK DIAGRAM
REF SELECT
D_CAPA
AV_DD
DV_DD
REF
BUF
AD7266
V_A1
V_A2
12-BIT
V_A3
V_A4
MUX
T/H
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
D_OUTA
V_A5
V_A6
SCLK
CS
RANGE
CONTROL
LOGIC
SGL/DIFF
A0
A1
V_B1
A2
V_B2
V_DRIVE
V_B3
MUX
12-BIT
V_B4
T/H
SUCCESSIVE
APPROXIMATION
OUTPUT
DRIVERS
D_OUTB
V_B5
ADC
V_B6
BUF
AGND AGND AGND D_CAPB
DGND DGND
Figure 1
PRODUCT HIGHLIGHTS
1. The AD7266 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
2. High Throughput with Low Power Consumption
The AD7266 offers a 1.5 MSPS throughput rate with 8 mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
4. No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a CS
input and once off conversion control.
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