AD7190 Datasheet, PDF (1/21 Pages) Analog Devices – 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA

Preliminary Technical Data
FEATURES
RMS Noise: 7 nV @ 4.7 Hz (gain = 128)
16.5 noise free bits @ 2.4 kHz (gain = 128)
Up to 23 noise free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 2 ppm/°C
Specified drift over time
Programmable gain (1 – 128)
Update rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Four general purpose digital outputs
Power supply: 3 V to 5.25 V
Current: 6 mA
Temperature range: –40°C to +105°C
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gauge transducers
Pressure measurement
Temperature measurement
Chromatography
4.8 kHz Ultra-Low Noise 24-Bit
Sigma-Delta ADC with PGA
AD7190
PLC/DCS Analog Input Modules
Data Acquisition
Medical and Scientific instrumentation
GENERAL DESCRIPTION
The AD7190 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise, 24-
bit ∑-∆ ADC. The on-chip low noise gain stage means that
signals of small amplitude can be interfaced directly to the
ADC.
The device can be configured to have two differential inputs or
four pseudo-differential inputs. The device can be operated
with either the internal clock or an external clock. The output
data rate from the part can be varied from 4.7 Hz to 4.8 kHz.
The device can be operated with a sinc³ or a sinc⁴ digital filter.
At the lower update rates, the sinc³ is useful to optimize the
settling time. The benefit of the sinc⁴ at low update rates is the
superior 50 Hz/60 Hz rejection. At the higher update rates, the
sinc⁴ filter gives best noise performance. For applications that
require all conversions to be settled, the AD7190 includes a
zero-latency feature.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 6 mA. It is housed in a 24-lead TSSOP
package.
AVDD
FUNCTIONAL BLOCK DIAGRAM
AGND
DVDD DGND
REFIN1(+) REFIN1(-)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AGND
AD7190
AVDD
MUX
PGA
SIGMA DELTA
ADC
AGND
TEMP
SENSOR
CLOCK
CIRCUITRY
REFERENCE
DETECT
SERIAL
INTERFACE
AND CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
MCLK1
MCLK2
Figure 1.
P0/REFIN2(-) P1/REFIN2(+)
Rev.PrD
7/08
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