AD7175-2 Datasheet, PDF (1/63 Pages) Analog Devices – 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

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24-Bit, 250 kSPS, Sigma-Delta ADC with
20 µs Settling and True Rail-to-Rail Buffers
AD7175-2
FEATURES
GENERAL DESCRIPTION
Fast and flexible output rate: 5 SPS to 250 kSPS
Channel scan data rate of 50 kSPS/channel (20 µs settling)
Performance specifications
17.2 noise free bits at 250 kSPS
20 noise free bits at 2.5 kSPS
24 noise free bits at 20 SPS
INL: ±1 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
2 fully differential channels or 4 single-ended channels
Crosspoint multiplexer
On-chip 2.5 V reference (±2 ppm/°C drift)
True rail-to-rail analog and reference input buffers
Internal or external clock
Power supply: AVDD1 = 5 V, AVDD2 = IOVDD = 2 V to 5 V
Split supply with AVDD1/AVSS at ±2.5 V
ADC current: 8.4 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI, MICROWIRE, and DSP
compatible
The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-
channel (fully/pseudo differential) Σ-Δ analog-to-digital
converter (ADC) for low bandwidth inputs. It has a maximum
channel scan rate of 50 kSPS (20 µs) for fully settled data. The
output data rates range from 5 SPS to 250 kSPS.
The AD7175-2 integrates key analog and digital signal condition-
ing blocks to allow users to configure an individual setup for
each analog input channel in use. Each feature can be user selected
on a per channel basis. Integrated true rail-to-rail buffers on the
analog inputs and external reference inputs provide easy to drive
high impedance inputs. The precision 2.5 V low drift (2 ppm/°C)
band gap internal reference (with output reference buffer) adds
embedded functionality to reduce external component count.
The digital filter allows simultaneous 50 Hz/60 Hz rejection at
27.27 SPS output data rate. The user can switch between
different filter options according to the demands of each
channel in the application. The ADC automatically switches
through each selected channel. Further digital processing
functions include offset and gain calibration registers,
configurable on a per channel basis.
APPLICATIONS
The device operates with a 5 V AVDD1, or ±2.5 V AVDD1/AVSS,
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
and 2 V to 5 V AVDD2 and IOVDD supplies. The specified
operating temperature range is −40°C to +105°C. The AD7175-2 is
in a 24-lead TSSOP package.
Chromatography
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function only.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
CROSSPOINT
MULTIPLEXER
1.8V
LDO
RAIL-TO-RAIL
REFERENCE
INPUT BUFFERS
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0
AIN1
AIN2
AIN3
AIN4
AVDD _RAIL-TO-RAIL
ANALOG INPUT
BUFFERS
Σ-Δ ADC
INT
REF
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
AVSS
TEMPERATURE
SENSOR
GPIO AND
MUX
I/O CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7175-2
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
AVSS
GPIO0 GPIO1
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
Rev. A
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