AD7002 Datasheet, PDF (1/16 Pages) Analog Devices – LC2MOS GSM Baseband I/O Port

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FEATURES
Single +5 V Supply
Transmit Channel
On-Chip GMSK Modulator
Two 10-Bit D/A Converters
Analog Reconstruction Filters
Power-Down Mode
Receive Channel
Two Sigma-Delta A/D Converters
FIR Digital Filters
On-Chip Offset Calibration
Power-Down Mode
3 Auxiliary D/A Converters
Power-Down Modes
On-Chip Voltage Reference
Low Power
44-Lead PQFP
APPLICATIONS
GSM
PCN
LC²MOS
GSM Baseband I/O Port
AD7002
GENERAL DESCRIPTION
The AD7002 is a complete low power, two-channel, input/
output port with signal conditioning. The device is used as a
baseband digitization subsystem, performing signal conversion
between the DSP and the IF/RF sections in the Pan-European
telephone system (GSM).
The transmit path consists of an onboard digital modulator,
containing all the code necessary for performing Gaussian Mini-
mum Shift Keying (GMSK), two high accuracy, fast DACs with
output reconstruction filters. The receive path is composed of
two high performance sigma-delta ADCs with digital filtering. A
common bandgap reference feeds the ADCs and signal DACs.
Three control DACs (AUX DAC1 to AUX DAC3) are in-
cluded for such functions as AFC, AGC and carrier signal shap-
ing. In addition, AUX FLAG may be used for routing digital
control information through the device to the IF/RF sections.
As it is a necessity for all GSM mobile systems to use the lowest
power possible, the device has power-down or sleep options for
all sections (transmit, receive and auxiliary).
The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack).
Tx SLEEP
Tx DATA
Tx CLK
THREE-STATE
ENABLE
Rx CLK
Rx DATA (I DATA)
Rx SYNC
I/Q (Q DATA)
RATE
MODE
AUX DATA
AUX CLK
AUX LATCH
Rx SLEEP1
Rx SLEEP2
FUNCTIONAL BLOCK DIAGRAM
DV_{DD DGND}
AV_{DD AGND}
GMSK PULSE
SHAPING ROM
10-BIT DAC
4TH ORDER BESSEL
LOW-PASS FILTER
AD7002
10-BIT DAC
2.5V
REFERENCE
4TH ORDER BESSEL
LOW-PASS FILTER
REFERENCE
OUTPUT BUFFER
RECEIVE
CHANNEL
SERIAL
INTERFACE
I CHANNEL
DIGITAL FIR FILTER
OFFSET REGISTER
OFFSET REGISTER
Q CHANNEL
DIGITAL FIR FILTER
Σ−∆ MODULATOR
SWITCH-CAP
FILTER
Σ−∆ MODULATOR
SWITCH-CAP
FILTER
I Tx
Q Tx
REF OUT
I Rx
Q Rx
16-BIT SHIFT REGISTER
9-BIT DAC 10-BIT DAC 8-BIT DAC
AUX
DAC 1
AUX
DAC 2
AUX
AUX
DAC 3 FLAG
CAL CLK2
CLK1 MZERO
REV. B
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 1997