AD6684 Datasheet, PDF (1/107 Pages) Analog Devices – 135 MHz Quad IF Receiver

Data Sheet
135 MHz Quad IF Receiver
AD6684
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 15 Gbps
1.68 W total power at 500 MSPS
420 mW per analog-to-digital converter (ADC) channel
SFDR = 82 dBFS at 305 MHz (1.8 V p-p input range)
SNR = 66.8 dBFS at 305 MHz (1.8 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.8 V p-p input range)
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
82 dB channel isolation/crosstalk
0.975 V, 1.8 V, and 2.5 V dc supply operation
Noise shaping requantizer (NSR) option for main receiver
Variable dynamic range (VDR) option for digital
predistortion (DPD)
4 integrated wideband digital downconverters (DDCs)
48-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, W-CDMA, GSM, LTE, LTE-A
HFC digital reverse path receivers
Digital predistortion observation paths
General-purpose software radios
AVDD1 AVDD1_SR
(0.975V) (0.975V)
FUNCTIONAL BLOCK DIAGRAM
AVDD2
(1.8V)
AVDD3
(2.5V)
DVDD DRVDD1 DRVDD2 SPIVDD
(0.975V) (0.975V) (1.8V)
(1.8V)
VIN+A
VIN–A
VCM_AB
FD_A
FD_B
VIN+B
VIN–B
CLK+
CLK–
VIN+C
VIN–C
VCM_CD
FD_C
FD_D
VIN+D
VIN–D
BUFFER
ADC
14
CORE
SIGNAL PROCESSING
DIGITAL DOWNCONVERTER
(×2)
FAST
DETECT
SIGNAL
MONITOR
BUFFER
ADC
14
CORE
NOISE SHAPED REQUANTIZER
(×2)
VARIABLE DYNAMIC RANGE
(×2)
JESD204B
HIGH SPEED
SERIALIZER
2
Tx
OUTPUTS
SIGNAL MONITOR
AND FAST DETECT
CLOCK
GENERATION
÷2
÷4
÷8
BUFFER
ADC
14
CORE
SIGNAL PROCESSING
DIGITAL DOWNCONVERTER
(×2)
FAST
DETECT
SIGNAL
MONITOR
NOISE SHAPED REQUANTIZER
(×2)
JESD204B
SUBCLASS 1
CONTROL
JESD204B
HIGH SPEED
SERIALIZER
2
Tx
OUTPUTS
BUFFER
ADC
14
CORE
VARIABLE DYNAMIC RANGE
(×2)
SPI CONTROL
AD6684
SERDOUTAB0±
SERDOUTAB1±
SYSREF±
SYNCINB±AB
SYNCINB±CD
SERDOUTCD0±
SERDOUTCD1±
PDWN/STBY
AGND DRGND SDIO SCLK CSB
Figure 1.
Rev. 0
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