AD6650_07 Datasheet, PDF (1/44 Pages) Analog Devices – AD6650 Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver

AD6650 Diversity IF-to-Baseband
GSM/EDGE Narrow-Band Receiver
AD6650
FEATURES
116 dB dynamic range
Digital VGA
I/Q demodulators
Active low-pass filters
Dual wideband ADC
Programmable decimation and channel filters
VCO and phase-locked loop circuitry
Serial data output ports
Intermediate frequencies of 70 MHz to 260 MHz
10 dB noise figure
+43 dBm input IP2 at 70 MHz IF
−9.5 dBm input IP3 at 70 MHz IF
3.3 V I/O and CMOS core
Microprocessor interface
JTAG boundary scan
APPLICATIONS
PHS or GSM/EDGE single carrier, diversity receivers
Microcell and picocell systems
Wireless local loop
Smart antenna systems
Software radios
In-building wireless telephony
PRODUCT DESCRIPTION
The AD6650 is a diversity intermediate frequency-to-baseband
(IF-to-baseband) receiver for GSM/EDGE. This narrow-band
receiver consists of an integrated DVGA, IF-to-baseband I/Q
demodulators, low-pass filtering, and a dual wideband ADC.
The chip can accommodate IF input from 70 MHz to 260 MHz.
The receiver architecture is designed such that only one external
surface acoustic wave (SAW) filter for main and one for diversity
are required in the entire receive signal path to meet GSM/EDGE
blocking requirements.
Digital decimation and filtering circuitry provided on-chip
remove unwanted signals and noise outside the channel of
interest. Programmable RAM coefficient filters allow antialiasing,
matched filtering, and static equalization functions to be combined
in a single cost-effective filter. The output of the channel filters
is provided to the user via serial output I/Q data streams.
AIN
VGA
AIN
CPOUT
LF
VLDO
PLL/
VCO
BIN
VGA
BIN
0
/4 90
FUNCTIONAL BLOCK DIAGRAM
TWEAK GAIN
DAC
I
LPF
MUX
LPF
Q
AGC
RELIN
CTRL
12-BIT
ADC
COARSE
DCC
LP
FILTER
4^TH
ORDER
CIC
7^TH
ORDER
IIR
REF
LPF
LPF
JTAG
Q
MUX
12-BIT
ADC
COARSE
DCC
I
DAC
TWEAK GAIN
CLK
DIVIDER
AGC
RELIN
CTRL
4^TH
ORDER
CIC
7^TH
ORDER
IIR
LP
FILTER
AD6650 GSM/
EDGE IF RECEIVER
PROG.
FIR
(RCF)
FINE
DCC
BIST
SERIAL
PORT
SCLK
SDFS
SDO0
SDO1
DR
PROG.
FIR
(RCF)
FINE
DCC
BIST
MICRO
Figure 1.
Rev. A
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