AD6634 Datasheet, PDF (1/52 Pages) Analog Devices – 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP)

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80 MSPS, Dual-Channel WCDMA
Receive Signal Processor (RSP)
AD6634
FEATURES
80 MSPS Wideband Inputs (14 Linear Bits Plus Three
RSSI)
Processes Two WCDMA Channels (UMTS or CDMA2000
1؋) or Four GSM/EDGE, IS136 Channels
Four Independent Digital Receivers in a Single Package
Dual 16-Bit Parallel Output Ports
Dual 8-Bit Link Ports
Programmable Digital AGC Loops with 96 dB Range
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Interpolating Half-Band Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers
GSM, IS136, EDGE, PHS, IS95, UMTS, CDMA2000
Micro and Pico Cell Systems, Software Radios
Wireless Local Loop
Smart Antenna Systems
In Building Wireless Telephony
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
SYNCA
SYNCB
SYNCC
SYNCD
I
N
P
U
T
M
A
T
R
I
X
EXTERNAL
SYNC.
CIRCUIT
FUNCTIONAL BLOCK DIAGRAM
rCIC2
RESAMPLER
CIC5
NCO
rCIC2
RESAMPLER
CIC5
NCO
rCIC2
RESAMPLER
CIC5
NCO
rCIC2
RESAMPLER
CIC5
NCO
JTAG
RAM
COEFFICIENT
FILTER
CHANNEL 0
RAM
COEFFICIENT
FILTER
CHANNEL 1
RAM
COEFFICIENT
FILTER
CHANNEL 2
RAM
COEFFICIENT
FILTER
CHANNEL 3
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
INTERPOLATING
HALF-BAND FILTER
PLUS
DIGITAL AGC
INTERPOLATING
HALF-BAND FILTER
PLUS
DIGITAL AGC
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
PORT A
LINK PORT
OR
PARALLEL
PORT
OUTPUT
MUX
CIRCUITRY
PORT B
LINK PORT
OR
PARALLEL
PORT
BUILT-IN (BIST)
SELF-TEST CIRCUITRY
MICROPORT OR SERIAL
PORT CONTROL
REV. 0
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© Analog Devices, Inc., 2002