AD6122_15 Datasheet, PDF (1/20 Pages) Analog Devices – CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator

a
CDMA 3 V Transmitter IF Subsystem
with Integrated Voltage Regulator
AD6122
FEATURES
range IF amplifiers with voltage-controlled gain and a power-
Fully Compliant with IS98A and PCS Specifications
down control input. An integral low dropout regulator allows
Linear IF Amplifier
operation from battery voltages from 2.9 V to 4.2 V.
–63 dB to +34 dB
The gain control input accepts an external gain control voltage
Linear-in-dB Gain Control
input from a DAC. It provides 97 dB of gain control with a
Temperature-Compensated Gain Control
nominal 75 dB/V scale factor. Either an internal or an external
Quadrature Modulator
reference may be used to set the gain-control scale factor.
Modulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10.4 mA at Midgain
<10 ␮A Sleep Mode Operation
E _{Companion Receiver IF Chip Available (AD6121)}
APPLICATIONS
CDMA, W-CDMA, AMPS and TACS Operation
T _{QPSK Transmitters}
GENERAL DESCRIPTION
E ^{The AD6122 is a low power IF transmitter subsystem, specifi-}
cally designed for CDMA applications. It consists of an I and Q
modulator, a divide-by-two quadrature generator, high dynamic
The I and Q modulator accepts differential quadrature base-
band inputs from a CDMA baseband converter. The local oscil-
lator is injected at twice the IF frequency. A divide-by-two
quadrature generator followed by dual polyphase filters ensures
± 1° quadrature accuracy.
The modulator provides a common-mode reference output to
bias the transmit DACs in the baseband converter to the same
common-mode voltage as the modulator inputs, allowing dc
coupling between the two ICs and thus eliminating the need to
charge and discharge coupling capacitors. This allows the fastest
power-up and power-down times for the AD6122 and CDMA
baseband ICs.
The AD6122 is fabricated using a 25 GHz f_t silicon BiCMOS
process and is packaged in a 28-lead SSOP and a 32-leadless
LPCC chip scale package (5 mm × 5 mm).
L FUNCTIONAL BLOCK DIAGRAM
VCC
OQUADRATURE
MODULATOR
OUTPUT
S _{I INPUT}
LOCAL
OSCILLATOR
BINPUT
QUADRATURE MODULATOR
،2
Q INPUT
COMMON-MODE
REFERENCE
O^OUTPUT
ATTENUATOR
AD6122
GAIN
IF AMPLIFIER
INPUT
IF AMPLIFIERS
TRANSMIT
OUTPUT
CONTROL
VPOS
LOW
DROPOUT
VREG
SCALE
FACTOR
TEMPERATURE
COMPENSATION
REGULATOR
POWER- POWER-
DOWN 1 DOWN 2
1.23 V
REFERENCE
GAIN CONTROL
REFERENCE
OUTPUT
VOLTAGE
INPUT
GAIN CONTROL
VOLTAGE
INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone]
© Analog Devices, Inc., 2000