AD608 Datasheet, PDF (1/12 Pages) Analog Devices – Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem

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Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
AD608
FEATURES
Mixer
–15 dBm 1 dB Compression Point
–5 dBm IP3
24 dB Conversion Gain
>500 MHz Input Bandwidth
Logarithmic/Limiting Amplifier
80 dB RSSI Range
؎3؇ Phase Stability over 80 dB Range
Low Power
21 mW at 3 V Power Consumption
CMOS-Compatible Power-Down to 300 ␮W typ
200 ns Enable/Disable Time
APPLICATIONS
PHS, GSM, TDMA, FM, or PM Receivers
Battery-Powered Instrumentation
Base Station RSSI Measurement
GENERAL DESCRIPTION
The AD608 provides both a low power, low distortion, low
noise mixer and a complete, monolithic logarithmic/limiting
amplifier using a “successive-detection” technique. It provides
both a high speed RSSI (Received Signal Strength Indicator)
output with 80 dB dynamic range and a hard-limited output.
The RSSI output is from a two-pole post-demodulation low-
pass filter and provides a loadable output voltage of +0.2 V to
+1.8 V. The AD608 operates from a single 2.7 V to 5.5 V sup-
ply at a typical power level of 21 mW at 3 V.
The RF and LO bandwidths both exceed 500 MHz. In a typical
IF application, the AD608 will accept the output of a 240 MHz
SAW filter and downconvert it to a nominal 10.7 MHz IF with
a conversion gain of 24 dB (Z_IF = 165 Ω). The AD608’s loga-
rithmic/limiting amplifier section handles any IF from LF to as
high as 30 MHz.
The mixer is a doubly-balanced “Gilbert-Cell” type and oper-
ates linearly for RF inputs spanning –95 dBm to –15 dBm. It
has a nominal –5 dBm third-order intercept. An onboard LO
preamplifier requires only –16 dBm of LO drive. The mixer’s
current output drives a reverse-terminated, industry-standard
10.7 MHz 330 Ω filter.
The nominal logarithmic scaling is such that the output is
+0.2 V for a sinusoidal input to the IF amplifier of –75 dBm
and +1.8 V at an input of +5 dBm; over this range the logarith-
mic conformance is typically ± 1 dB. The logarithmic slope is
proportional to the supply voltage. A feedback loop automati-
cally nulls the input offset of the first stage down to the sub-
microvolt level.
The AD608’s limiter output provides a hard-limited signal out-
put at 400 mV p-p. The voltage gain of the limiting amplifier to
this output is more than 100 dB. Transition times are 11 ns and
the phase is stable to within ± 3° at 10.7 MHz for signals from
–75 dBm to +5 dBm.
The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 µW within 400 ns.
The AD608 is specified for the industrial temperature range of
–25°C to +85°C for 2.7 V to 5.5 V supplies and –40°C to +85°C
for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC.
FUNCTIONAL BLOCK DIAGRAM
24dB MIXER GAIN
3dB NOMINAL
INSERTION LOSS
110dB LIMITER GAIN
90dB RSSI
RFHI 5
RF INPUT
–95 TO
–15dBm¹
RFLO 6
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
MIXER
≈
LO
PREAMP
MXOP
7
BPF
DRIVER
VMID
8
REV. B
LOHI
MID-SUPPLY
IF BIAS
BIAS
VPS1 COM1
COM2
PRUP
1
23
4 16
+2.7V TO
5.5V
LO INPUT CMOS LOGIC
–16dBm
INPUT
IF INPUT
–75dBm TO
+15dBm²
10.7MHz
BANDPASS
FILTER
IFHI
9
330Ω
100nF
330Ω
10nF
100Ω
10
IFLO
18nF
13
FDBK
7 FULL-WAVE
RECTIFIER CELLS
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
≈
RSSI
RSSI OUTPUT
11 ^20mV/dB
0.2V TO 1.8V
2MHz
LPF
COM3 12
VPS2
14
+2.7V TO 5.5V
LMOP
15
FINAL
LIMITER
LIMITER
OUTPUT
400mVp-p
AD608
±50µA
NOTES:
1 _{–15dBm = ±56mV MAX FOR LINEAR OPERATION}
2 _{39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI}
ACCURACY
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone]