AD5686R Datasheet, PDF (1/32 Pages) Analog Devices – Quad, 16-/14-/12-Bit nanoDAC

Data Sheet
Quad, 16-/14-/12-Bit nanoDAC+
with 2 ppm/°C Reference, SPI Interface
AD5686R/AD5685R/AD5684R
FEATURES
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base-station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5686R/AD5685R/AD5684R, members of the
nanoDAC+® family, are low power, quad, 16-/14-/12-bit
buffered voltage output DACs. The devices include a 2.5 V,
2 ppm/°C internal reference (enabled by default) and a gain
select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V
(gain = 2). All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design, and exhibit less
than 0.1% FSR gain error and 1.5 mV offset error performance.
The devices are available in a 3 mm × 3 mm LFCSP and a
TSSOP package.
The AD5686R/AD5685R/AD5684R also incorporate a power-
on reset circuit and a RSTSEL pin that ensures that the DAC
outputs power up to zero scale or midscale and remains there
until a valid write takes place. Each part contains a per-channel
power-down feature that reduces the current consumption of
the device to 4 μA at 3 V while in power-down mode.
The AD5686R/AD5685R/AD5684R employ a versatile SPI
interface that operates at clock rates up to 50 MHz, and all
devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
Rev. 0
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FUNCTIONAL BLOCK DIAGRAM
V_DD
GND
V_REF
V_LOGIC
SCLK
SYNC
SDIN
SDO
AD5686R/AD5685R/AD5684R
2.5V
REFERENCE
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
INPUT
REGISTER
DAC
STRING
REGISTER DAC C
INPUT
REGISTER
DAC
STRING
REGISTER DAC D
POWER-ON
RESET
GAIN
×1/×2
BUFFER
V_OUTA
BUFFER
V_OUTB
BUFFER
V_OUTC
BUFFER
POWER-
DOWN
LOGIC
V_OUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI
Internal AD5686R
I²C
Internal AD5696R
14-Bit 12-Bit
AD5685R AD5684R
AD5695R AD5694R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5686R (16-bit): ±2 LSB maximum
AD5685R (14-bit): ±1 LSB maximum
AD5684R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
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