AD5678 Datasheet, PDF (1/28 Pages) Analog Devices – 4 × 12-Bit and 4 × 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP

4 × 12-Bit and 4 × 16-Bit Octal DAC with
On-Chip Reference in 14-Lead TSSOP
AD5678
FEATURES
Low power octal DAC with
Four 16-bit DACs
Four 12-bit DACs
14-lead/16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
3 power-down functions
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5678 is a low power, octal, buffered voltage-output
DAC with four 12-bit DACs and four 16-bit DACs in a single
package. All devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design.
The AD5678 has an on-chip reference with an internal gain of 2.
The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-
scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V and remains powered up at
this level until a valid write takes place. The part contains a
power-down feature that reduces the current consumption of
the device to 400 nA at 5 V and provides software-selectable
output loads while in power-down mode for any or all DAC
channels.
FUNCTIONAL BLOCK DIAGRAM
AD5678
LDAC
SCLK
SYNC
DIN
INTERFACE
LOGIC
LDAC¹ CLR1
1_{RU-16 PACKAGE ONLY}
V_DD
V_REFIN/V_REFOUT
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
1.25V/2.5V
REF
STRING
DAC A
BUFFER
STRING
DAC B
BUFFER
STRING
DAC C
BUFFER
STRING
DAC D
BUFFER
STRING
DAC E
BUFFER
STRING
DAC F
BUFFER
STRING
DAC G
BUFFER
STRING
DAC H
BUFFER
POWER-DOWN
LOGIC
GND
Figure 1.
V_OUTA
V_OUTB
V_OUTC
V_OUTD
V_OUTE
V_OUTF
V_OUTG
V_OUTH
The outputs of all DACs can be updated simultaneously using
the LDAC function, with the added functionality of user-
selectable DAC channels to simultaneously update. There is
also an asynchronous CLR that clears all DACs to a software-
selectable code—0 V, midscale, or full scale.
The AD5678 utilizes a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables rail-
to-rail output swing.
PRODUCT HIGHLIGHTS
1. Octal DAC (four 12-bit DACs and four 16-bit DACs).
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 14-lead/16-lead TSSOP.
4. Power-on reset to 0 V.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
Rev. A
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