AD5676 Datasheet, PDF (1/28 Pages) Analog Devices – Easy implementation

Data Sheet
Octal, 16-Bit nanoDAC+ with SPI Interface
AD5676
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, TSSOP and LFCSP RoHS-compliant packages
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
The AD5676 is a low power, octal, 16-bit buffered voltage
output digital-to-analog converter (DAC). The device includes
a gain select pin, giving a full-scale output of VREF (gain = 1) or
2 × VREF (gain = 2). The AD5676 DAC operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5676 is available in 20-lead TSSOP and LFCSP packages.
The internal power-on reset circuit and the RSTSEL pin of the
AD5676 ensure that the output DACs power up to zero scale or
midscale and then remain there until a valid write takes place. The
AD5676 contains a per channel power-down mode that typically
reduces the current consumption of the device to 1 µA.
The AD5676 employs a versatile serial peripheral interface (SPI)
that operates at clock rates up to 50 MHz, and contains a VLOGIC pin
intended for 1.8 V to 5.5 V logic.
Table 1. Octal nanoDAC+® Devices
Interface Reference 16-Bit
SPI
Internal
AD5676R
External
AD5676
I²C
Internal
AD5675R
External
AD5675
12-Bit
AD5672R
Not applicable
AD5671R
Not applicable
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL) 16-bit: ±3 LSB maximum.
2. −40°C to +125°C temperature range.
3. 20-lead, TSSOP and LFCSP RoHS-compliant packages.
FUNCTIONAL BLOCK DIAGRAM
V_LOGIC
V_DD
V_REF
AD5676
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 0
BUFFER
V_OUT0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
BUFFER
V_OUT1
SCLK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
BUFFER
V_OUT2
SYNC
SDI
INTERFACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC 3
STRING
DAC 4
BUFFER
BUFFER
V_OUT3
V_OUT4
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
BUFFER
V_OUT5
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
BUFFER
V_OUT6
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
BUFFER
V_OUT7
POWER-ON RESET
GAIN x1/x2
POWER-DOWN
LOGIC
RSTSEL
GAIN
GND
Figure 1.
Rev. B
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