AD5672R Datasheet, PDF (1/34 Pages) Analog Devices – Octal, 12-/16-Bit nanoDAC+ with ppm/°C Reference, SPI Interface

Data Sheet
Octal, 12-/16-Bit nanoDAC+ with
2 ppm/°C Reference, SPI Interface
AD5672R/AD5676R
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply range
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, RoHS-compliant TSSOP and LFCSP
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
The AD5672R/AD5676R are low power, octal, 12-/16-bit buffered
voltage output digital-to-analog converters (DACs). They include
a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a
gain select pin giving a full-scale output of 2.5 V (gain = 1) or
5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V
supply and are guaranteed monotonic by design. The AD5672R/
AD5676R are available in a 20-lead TSSOP and in a 20-lead LFCSP
and incorporate a power-on reset circuit and a RSTSEL pin that
ensures that the DAC outputs power up to zero scale or midscale
and remain there until a valid write. The AD5672R/AD5676R
contain a power-down mode, reducing the current consumption to
1 µA typical while in power-down mode.
Table 1. Octal nanoDAC+® Devices
Interface
Reference
16-Bit
SPI
Internal
AD5676R
External
AD5676
I²C
Internal
AD5675R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5672R (12-bit): ±1 LSB maximum.
AD5676R (16-bit): ±3 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
12-Bit
AD5672R
Not applicable
AD5671R
FUNCTIONAL BLOCK DIAGRAM
V_LOGIC
V_DD
V_REFOUT
AD5672R/AD5676R
SCLK
SYNC
SDI
SDO
LDAC
RESET
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
2.5V
REF
STRING
DAC 0
BUFFER
STRING
DAC 1
BUFFER
STRING
DAC 2
BUFFER
STRING
DAC 3
BUFFER
STRING
DAC 4
BUFFER
STRING
DAC 5
BUFFER
STRING
DAC 6
BUFFER
STRING
DAC 7
BUFFER
V_OUT0
V_OUT1
V_OUT2
V_OUT3
V_OUT4
V_OUT5
V_OUT6
V_OUT7
POWER-ON
RESET
GAIN POWER-DOWN
×1/×2
LOGIC
RSTSEL
Figure 1.
GAIN
GND
Rev. B
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