AD5628 Datasheet, PDF (1/24 Pages) Analog Devices – Octal, 12-14-16 Bit Dac with 10ppm/°C Max On-Chip Reference in 14-Lead TSSOP

Octal, 12-14-16 Bit Dac with 10ppm/°C Max
On-Chip Reference in 14-Lead TSSOP
Preliminary Technical Data
AD5628/AD5648/AD5668
FEATURES
Low Power Smallest Pin compatible Octal DACs
AD5668: 16 Bits
AD5648: 14 Bits
AD5628: 12 Bits
12-Bit Accuracy Guaranteed
14/16-Lead TSSOP Package
On-chip 1.25/2.5V, 10ppm/°C Reference
Power-Down to 200 nA @ 5V, 50 nA @ 3V
3V/5V Power Supply
Guaranteed Monotonic by Design
Power-On-Reset to Zero/Midscale
Three Power-Down Functions
Hardware /LDAC and /CLR functions
Rail-to-Rail Operation
Temperature Range -40°C to +125°C
APPLICATIONS
ProcessControl
Data Acquisition Systems
Portable Battery Powered Instruments
GENERAL DESCRIPTION
The AD5628/48/68 family of devices are low power, octal, 12-
14-16-bit buffered voltage-out DACs. All devices operate from
a single +2.7V to +5.5V, and are guaranteed monotonic by
design.
The AD5628/48/68 have an on-chip reference with an internal
gain of two. The AD56x8-1 has a 1.25V 10ppm/°C max
reference and the AD56x8-2,-3 have a 2.5V 10ppm/°C max
reference. The on-board reference is off at power-up allowing
the use of an external reference. The internal reference is
turned on by writing to the DAC. The part incorporates a
power-on-reset circuit that ensures that the DAC output
powers up to zero volts (AD56x8-1,-2/) or midscale (AD5668-
3) and remains there until a valid write takes place. The part
contains a power-down feature that reduces the current
consumption of the device to 200nA at 5V and provides
software selectable output loads while in power-down mode for
any or all DACs channels.
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
VDD
V_REF
AD5628/AD5648/AD5668
L DA C
SCLK
SYNC
DIN
INTERFACE
L OGIC
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGIS-
TER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
1.25/2.5V
Ref
STRING
DAC A
BUFFER
DA C
REGISTER
STRING
DAC B
DAC
REGISTER
STRING
DAC C
DA C
REGISTER
DA C
REGISTER
STRING
DAC D
STRING
DAC E
DA C
REGISTER
STRING
DAC F
DA C
REGISTER
STRING
DAC G
DA C
REGISTER
STRING
DAC H
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
LDAC* CLR*
*RU-16 PACKAGE ONLY
POWER-ON
RESET
POWER-DOWN
LOGIC
GND
Figure 1. Functional Block Diagram
The outputs of all DACs may be updated simultaneously using
the /LDAC function, with the added functionality of selecting
through software any number of DAC channels to synchronize.
There is also an asynchronous active low /CLR that clears all
DACs to a software selectable code - 0 V, midscale or fullscale .
The AD5628/48/68 utilizes a versatile three-wire serial
interface that operates at clock rates up to 50 MHz and is
compatible with standard SPI™, QSPI™, MICROWIRE™ and
DSP interface standards. Its on-chip precision output amplifier
allows rail-to-rail output swing to be achieved.
PRODUCT HIGHLIGHTS
1. Octal 12/14/16-Bit DAC; 12-Bit Accuracy Guaranteed.
2. On-chip 1.25/2.5V, 10ppm/°C max Reference.
3. Available in 14/16-lead TSSOP package.
4. Power-On-Reset to Zero volts or Midscale.
5. Power-down capability. When powered down, the
DAC typically consumes 50nA at 3V and 200nA at 5V.
Rev. PrA
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