AD5602 Datasheet, PDF (1/24 Pages) Analog Devices – 2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with

2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDACs^® with
I²C^®-Compatible Interface, Tiny SC70 Package
AD5602/AD5612/AD5622
FEATURES
Single 8-, 10-, 12-bit DACs, 2 LSB INL
6-lead SC70 package
Micropower operation: 100 μA max @ 5 V
Power-down to <150 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
I²C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
On-chip output buffer amplifier, rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5602/AD5612/AD5622, members of the nanoDAC
family, are single 8-, 10-, 12-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply, consuming <100 μA
at 5 V. These DACs come in tiny SC70 packages. Each DAC
contains an on-chip precision output amplifier that allows rail-
to-rail output swing to be achieved.
The AD5602/AD5612/AD5622 use a 2-wire I²C-compatible
serial interface that operates in standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) modes.
The references for AD5602/AD5612/AD5622 are derived from
the power supply inputs to give the widest dynamic output range.
Each part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place to the device. The parts contain a power-down
feature that reduces the current consumption of the devices to
<150 nA at 3 V and provides software-selectable output loads
while in power-down mode. The parts are put into power-down
mode over the serial interface. The low power consumption of
the AD5602/AD5612/AD5622 in normal operation makes them
ideally suited for use in portable battery-operated equipment. The
typical power consumption is 0.4 mW at 5 V.
FUNCTIONAL BLOCK DIAGRAM
V_{DD GND}
POWER-ON
RESET
AD5602/AD5612/AD5622
DAC
REGISTER
REF(+)
8-/10-/12-BIT
DAC
OUTPUT
BUFFER
V_OUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
ADDR SCL SDA
Figure 1.
Table 1. Related Devices
Part No.
AD5601/AD5611/AD5621
Description
2.7 V to 5.5 V, <100 μA, 8-, 10-, 12-bit
nanoDAC with SPI® interface in a
tiny SC70 package
PRODUCT HIGHLIGHTS
1. Available in a 6-lead SC70 package.
2. Maximum 100 μA power consumption, single-supply
operation. These parts operate from a single 2.7 V to 5.5 V
supply, typically consuming 0.2 mW at 3 V and 0.4 mW at
5 V, making them ideal for battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/μs.
4. Reference derived from the power supply.
5. Standard, fast, and high speed mode I²C interface.
6. Designed for very low power consumption.
7. Power-down capability. When powered down, the DAC
typically consumes <150 nA at 3 V.
8. Power-on reset and brownout detection.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
www.analog.com
Fax: [phone]
©2006 Analog Devices, Inc. All rights reserved.