AD5582 Datasheet, PDF (1/8 Pages) Analog Devices – QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter

PRELIMINARY TECHNICAL DATA
a
QUAD, Parallel-Input, Voltage Output,
12-/10-Bit Digital-to-Analog Converter
AD5582/AD5583
FEATURES
12-Bit Linearity and Monotonic –40^oC to +125^oC
Single +5V to +12V or dual ±5V supply
Unipolar or Bipolar Operation
Double Buffered Registers Enable Simultaneous Multi-
Channels Update
4 Separate Rail-to Rail Reference Inputs
Parallel Interface
Data Readback Capability
5µs Settling Time
APPLICATIONS
Process Control Equipment
Closed Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Motor Control
Optical Network Control Loops
GENERAL DESCRIPTION
The AD5582/AD5583 family of quad, 12-/10-bit, voltage-output
digital-to-analog converter is designed to operate from a single +5
to +15 volt or a dual ±5V supply. Built using a CBCMOS process,
this monolithic DAC offers the user low cost, and ease-of-use in
single or dual-supply systems.
The applied external reference V_REF determines the full-scale
output voltage. Valid V_REF values include V_SS<V_REF<V_DD resulting
in a wide selection of full scale outputs. For multiplying
applications AC inputs can be as large as |V_DD-V_SS|. Two on-board
precision trimmed resistors are available for 4-Quadrant
configurations.
A doubled-buffered parallel interface offers 25Mbps data load rates.
A common level-sensitive load-DAC strobe (LDAC) input allows
simultaneous update of all DAC outputs from previously loaded
Input Registers. An external asynchronous reset (RS) forces all
registers to the zero code state when MSB='0' or to midscale when
MSB='1'.
Both parts are offered in the same pin-out to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.
The AD5582/AD5583 are specified over the extended industrial
(-40°C to +125°C) temperature range. Packages available include
thin 1.1 mm TSSOP-48 package.
FUNCTIONAL DIAGRAM
A1 37
A0 36
ADDR
DECODE
DB11 24
DB10 25
I
DB9 26
N
DB8 27
T
E
DB7 28
R
DB6 29
F
DB5 30
A
C
DB4 ³¹
E
DB3 32
Do
Di
IN
REG
DB2 ³³
DB1 34
OE
DB0 35
CS ²³
W/R 22
VLOGIC 19
CONTROL
L OGIC
MSB 17
RS ¹⁸
LDAC 21
16
20
DVDD
DGND
VRLA VRHA VRLB VRHBVDD
1
2
3
4
5
DAC
REG
6 VOA
7 VOB
20kΩ
20kΩ
AD5582
38 RA
39 RB
40 RC
8 _AGND
9 VOC
10 VOD
15
14
13
12
11
VRHDVRLD VRHCVRLCVSS
+2.5V
ADR421
R_A
R_B
R_C
-2.5V
V _REFH
A
B
C
D
AD5582
DAC A
V _REFL
A
B
C
D
DAC B
DAC C
DAC D
±2.5V
±2.5V
±2.5V
±2.5V
DIG ITAL CIRCUITRY O MITTED FO R CLARITY
Figure 1 Using Onboard Offset resistors to generate a negative
voltage REF
REV PrC, 23 APR '01
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