AD5544_04 Datasheet, PDF (1/20 Pages) Analog Devices – Quad, Current-Output, Serial-Input 16-/14-Bit DACs

FEATURES
AD5544 16-bit resolution
AD5554 14-bit resolution
2 mA full-scale current ±20%, with VREF = ±10 V
2 µs settling time
VSS BIAS for zero-scale error reduction @ temp
midscale or zero-scale reset
Four separate, 4-Q multiplying reference inputs
SPI®-compatible 3-wire interface
Double buffered registers enable
Simultaneous multichannel change
Internal power ON reset
Compact SSOP-28 package
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital
to-analog converters are designed to operate from a single
5 V supply.
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
A double-buffered serial-data interface offers high speed,
3-wire, SPI- and microcontroller-compatible inputs using serial-
data-in (SDI), a chip-select (CS), and clock (CLK) signals. In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common, level-sensitive,
load-DAC strobe (LDAC) input allows the simultaneous update
of all DAC outputs from previously loaded input registers.
Additionally, an internal power ON reset forces the output
voltage to zero at system turn ON. An MSB pin allows system
reset assertion (RS) to force all registers to zero code when
MSB = 0, or to half-scale code when MSB = 1.
The AD5544/AD5554 are packaged in the compact SSOP-28.
Rev. A
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Quad, Current-Output,
Serial-Input 16-/14-Bit DACs
AD5544/AD5554
SDO
SDI
CS
CLK
FUNCTIONAL BLOCK DIAGRAM
V_REFA B C D
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 16
D10
D11
D12
D13
D14
D15
A0
A1
INPUT
REGISTER R
DAC A
REGISTER R
INPUT
REGISTER R
DAC B
REGISTER R
INPUT
REGISTER R
DAC C
REGISTER R
DAC A
DAC B
DAC C
EN
DAC A
B
C
D
2:4
DECODE
DGND
INPUT
REGISTER R
DAC D
REGISTER R
DAC D
POWER-
ON
RESET
RS MSB
LDAC
Figure 1.
AD5544
VSS
V_DD
R_FBA
I_OUTA
A_GNDA
R_FBB
I_OUTB
A_GNDB
R_FBC
I_OUTC
A_GNDC
R_FBD
I_OUTD
A_GNDD
A_GNDF
1.0
0.5
0
–0.5
–1.0
1.0
0.5
0
–0.5
–1.0
1.0
0.5
0
–0.5
–1.0
1.0
0.5
0
–0.5
–1.0
0
DAC A
DAC B
DAC C
DAC D
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
Figure 2. AD5544 INL vs. Code Plot (TA = 25°C)
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