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AD5441 Datasheet, PDF (1/16 Pages) Analog Devices – 12-Bit Serial Input Multiplying DAC
Preliminary Technical Data
FEATURES
3 V to 5 V supply operation
True 12-bit accuracy
5 V operation @ <10 μA
Fast 3-wire serial input
Fast 1 μs settling time
2.4 MHz, 4-quadrant multiply BW
Upgrade for DAC8043 and DAC8043A
Standard and rotated pinout
APPLICATIONS
Ideal for PLC applications in industrial control
Programmable amplifiers and attenuators
Digitally controlled calibration and filters
Motion control systems
GENERAL DESCRIPTION
The AD5441 is an improved high accuracy 12-bit multiplying
digital-to-analog converter (DAC) in space-saving 8-lead
packages. Featuring serial input, double buffering, and excellent
analog performance, the AD5441 is ideal for applications where
PC board space is at a premium. Improved linearity and gain
error performance permit reduced part counts through the
elimination of trimming components. Separate input clock and
load DAC control lines allow full user control of data loading
and analog output.
The circuit consists of a 12-bit serial-in/parallel-out shift
register, a 12-bit DAC register, a 12-bit CMOS DAC, and
control logic. Serial data is clocked into the input register on the
rising edge of the CLOCK pulse. When the new data-word is
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the DAC.
Consuming only 10 μA from a single 5 V power supply, the
AD5441 is the ideal low power, small size, high performance
solution to many application problems.
The AD5441 is specified over the extended industrial (−40°C to
+125°C) temperature range. It is available in an 8-lead LFCSP
and an 8-lead MSOP.
12-Bit Serial Input
Multiplying DAC
AD5441
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
LD
AD5441
DAC
12
DAC REG
RFB
IOUT
CLK
SRI
12
12-BIT SHIFT
REGISTER
GND
Figure 1.
0.5
TA = –40°C, +25°C, +85°C
0.4 VDD = +5V
VREF = –10V
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 2. Integral Nonlinearity Error vs. Code
Rev. PrA
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