AD5425_15 Datasheet, PDF (1/25 Pages) Analog Devices – 8-Bit, High Bandwidth Multiplying DAC with Serial Interface

Data Sheet
8-Bit, High Bandwidth
Multiplying DAC with Serial Interface
AD5425
FEATURES
GENERAL DESCRIPTION
2.5 V to 5.5 V supply operation
50 MHz serial interface
2.47 MSPS update rate
INL of ±0.25 LSB
10 MHz multiplying bandwidth
±10 V reference input
The AD5425¹ is a CMOS, 8-bit, current output digital-to-analog
converter that operates from a 2.5 V to 5.5 V power supply,
making it suitable for battery-powered applications and many
other applications.
This DAC utilizes a double buffered, 3-wire serial interface that
Low glitch energy: <2 nV-s
Extended temperature range: −40°C to +125°C
10-lead MSOP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. An LDAC pin is also provided, which
allows simultaneous updates in a multi-DAC configuration. On
power-up, the internal shift register and latches are filled with
0s and the DAC outputs are 0 V.
LDAC function
As a result of manufacturing on a CMOS submicron process,
0.4 µA typical power consumption
this DAC offers excellent 4-quadrant multiplication charac-
teristics with large signal multiplying bandwidths of 10 MHz.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
The applied external reference input voltage (V_REF) determines
the full-scale output current. An integrated feedback resistor,
R_FB, provides temperature tracking and full-scale voltage output
when combined with an external I-to-V precision amplifier.
The AD5425 is available in a small, 10-lead MSOP package.
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V_DD
V_REF
AD5425
8-BIT
R-2R DAC
R
R_FB
I_OUT1
I_OUT2
LDAC
POWER-ON
RESET
DAC REGISTER
INPUT LATCH
SYNC
SCLK
SDIN
CONTROL LOGIC AND
INPUT SHIFT REGISTER
GND
Figure 1.
1 _{U.S. Patent No. 5,969,657.}
Rev. C
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