AD5383_15 Datasheet, PDF (1/40 Pages) Analog Devices – 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC

Data Sheet
32-Channel, 3 V/5 V, Single-Supply,
12-Bit, denseDAC
AD5383
FEATURES
Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
I²C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical microelectro-mechanical systems (MEMS)
Control systems
Instrumentation
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I²C)
DB8
DB0
A4
A0
REG 0
REG 1
RESET
BUSY
CLR
MON_IN1
MON_IN2
MON_IN3
MON_IN4
DV_DD (×3)
DGND (×3)
FUNCTIONAL BLOCK DIAGRAM
AV_DD (×4)
AGND (×4) DAC GND (×4)
REFGND
REFOUT/REFIN SIGNAL GND (×4)
AD5383
1.25V/2.5V
REFERENCE
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
POWER-ON
RESET
V_OUT0………V_OUT31
36-TO-1
MUX
12 _INPUT 12
REG 0
12
m REG 0
12
c REG 0
12 _INPUT 12
REG 1
12
m REG 1
12
c REG 1
12 _INPUT 12
REG 6
12
m REG 6
12
c REG 6
12 _INPUT 12
REG 7
12
m REG 7
12
c REG 7
×4
12
DAC ¹²
REG 0
DAC 0
12
DAC ¹²
REG 1
DAC 1
12
DAC ¹²
REG 6
DAC 6
12
DAC ¹²
REG 7
DAC 7
R
R
R
R
R
R
R
R
V_OUT0
V_OUT1
V_OUT2
V_OUT3
V_OUT4
V_OUT5
V_OUT6
V_OUT7
V_OUT8
V_OUT31
MON_OUT
Figure 1.
LDAC
Rev. D
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