AD5382_15 Datasheet, PDF (1/40 Pages) Analog Devices – 32-Channel, 3 V/5 V, Single-Supply, 14-Bit denseDAC

Data Sheet
32-Channel, 3 V/5 V, Single-Supply,
14-Bit denseDAC
AD5382
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User interfaces
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
I²C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
DVDD (×3)
DGND (×3)
FUNCTIONAL BLOCK DIAGRAM
AVDD (×4)
AGND (×4) DAC_GND (×4)
REFGND REFOUT/REFIN SIGNAL_GND (×4)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I²C)
DB10
DB0
A4
A0
REG0
REG1
RESET
BUSY
CLR
AD5382
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
POWER-ON
RESET
VOUT0………VOUT31
MON_IN1
MON_IN2
MON_IN3
MON_IN4
36-TO-1
MUX
14 _INPUT 14
REG0
14
14
m REG0
c REG0
14 _INPUT 14
REG1
14
14
m REG1
c REG1
14 _INPUT 14
REG6
14
14
m REG6
c REG6
14 _INPUT 14
REG7
14
14
m REG7
c REG7
×4
1.25V/2.5V
REFERENCE
14
DAC ¹⁴
REG0
DAC 0
14
DAC ¹⁴
REG1
DAC 1
14
DAC ¹⁴
REG6
DAC 6
14
DAC ¹⁴
REG7
DAC 7
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT31
MON_OUT
Figure 1.
LDAC
Rev. D
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