AD5380 Datasheet, PDF (1/34 Pages) Analog Devices – 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC

PRELIMINARY TECHNICAL DATA
a
40-Channel, 3V/5V Single Supply,
14-Bit, Voltage-Output DAC
Preliminary Technical Data
AD5380
FEATURES
GENERAL DESCRIPTION
Guaranteed Monotonic
The AD5380 is a complete single supply, 40-channel, 14-
INL Error: ±4LSB max
bit DAC available in 100-lead LQFP package. All
On-Chip 1.25/2.5V, 10ppm/°C Reference
40-channels have an on-chip output amplifier with rail-to-
Temperature Range: -40°C to +85°C
rail operation. The AD5380 includes an internal 1.25/
Rail to Rail Output Amplifier
2.5V, 10ppm/°C reference, an on-chip channel monitor
Package Type: 100-lead LQFP (14mm x 14mm)
function that multiplexes the analog outputs to a common
User Interfaces:
MON_OUT pin for external monitoring and an output
Parallel,
amplifier boost mode that allows the amplifier settling
Serial (SPI, QSPI, Microwire and DSP compatible
featuring Data Readback)
I2C Compatible Interface
INTEGRATED FUNCTIONS
time to be optimized. The AD5380 contains a double
buffered parallel interface featuring a WR pulse width of
20ns, a serial interface compatible with SPI^TM, QSPI^TM,
MICROWIRE^TM and DSP interface standards with
Channel Monitor
Simultaneous Output Update via LDAC
interface speeds in excess of 30MHz and an I2C
compatible interface supporting 400kHz data transfer rate.
Clear Function to User Programmable Code
Amplifier Boost Mode to Optimize Slew Rate
User Programmable Offset and Gain Adjust
Toggle Mode: Enables Squarewave Generation
An input register followed by a DAC register provides
double buffering allowing the DAC outputs to be updated
independantly or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
APPLICATIONS
Variable Optical Attenuators (VOA)
register allowing the user to fully calibrate any DAC Channel.
Power consumption is typically 0.3mA/channel.
Level Setting
Optical Microelectromechanical Systems (MEMs)
Control Systems
FUNCTIONAL BLOCK DIAGRAM
DVDD (X3) DGND (X3) AVDD (X5) AGND (X5) DAC GND (X5)
REFGND
REFOUT/ REFIN SIGNAL GND (X5)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO(A/B)
DB13 /(DIN/SDA)
DB12 /(SCLK/SCL)
DB11 /(SPI/I2C)
DB.10
DB0
A5
A0
REG0
REG1
RESET
BUSY
CLR
AD5380
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
POWER-ON
RESET
14 INPUT ₁₄
REG
0
X+
14
m REG0
14
c REG0
14 INPUT
REG
1
. ₁₄
.
. ¹⁴
.
.
14 INPUT
REG
6
14
14
14
X
m REG1
c RE_. G1
.
.
14 ^.
.X
m REG6
c REG6
2.5V
Reference
14 DAC 14
REG
DAC 0
0
14
+
14
+
DAC 14
REG
1_.
.
.
.
.
DAC 1
.
.
.
DAC 14
REG
DAC 6
6
+
-
R
R
+
-
R
R.
.
.
+
-
R
R
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 0 .......... VOUT 38
39 -TO-1
MUX
14 INPUT ₁₄
REG
X+
7
14
m REG7
14
c REG7
14
X5
DAC 14
REG DAC 7
7
+
-
R
R
VOUT 7
VOUT 8
VOUT 38
VOUT 39 / MON_OUT
*Protected by U.S. Patent Nos. 5,969,657; other patents pending.
SPI and QSPI are Trademarks of Motorola, Inc.
MICROWIRE is a Trademark of National Semiconductor Corporation.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
LDAC
REV. PrF 09/2003
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© Analog Devices, Inc., 2003