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AD5363_15 Datasheet, PDF (1/29 Pages) Analog Devices – 8-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC
FEATURES
8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output voltage spans available
Thermal shutdown function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
8-Channel, 16-/14-Bit,
Serial Input, Voltage Output DAC
AD5362/AD5363
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
TEMP_OUT
PEC
MON_IN0
MON_IN1
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DGND
LDAC
TEMP
SENSOR
8
CONTROL
REGISTER
VOUT0 TO
VOUT7
6
n = 16 FOR AD5362
n = 14 FOR AD5363
8 A/B SELECT 8
REGISTER
MUX
n X1 REGISTER n
n M REGISTER n
GPIO
REGISTER
n
2
C REGISTER n
···
···
SERIAL
INTERFACE
n
n
X1 REGISTER
n M REGISTER n
n C REGISTER n
STATE
MACHINE
n
AD5362/
AD5363
8 A/B SELECT 8
REGISTER
n X1 REGISTER n
n M REGISTER n
n C REGISTER n
···
···
n X1 REGISTER n
n M REGISTER n
n C REGISTER n
14
TO
MUX 2s
n A/B
MUX
X2A REGISTER
X2B REGISTER
n
MUX
2
··· ···
n A/B
MUX
·
·
·
X2A REGISTER
X2B REGISTER
n
MUX
2
14
TO
MUX 2s
n A/B
MUX
X2A REGISTER
X2B REGISTER
n
MUX
2
·
··· ···
·
·
n A/B
MUX
X2A REGISTER
X2B REGISTER
n
MUX
2
OFS0 14
REGISTER
DAC 0 n
REGISTER
OFFSET
DAC 0
DAC 0
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
·
·
·
·
·
·
·
·
·
DAC 3 n
REGISTER
DAC 3
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OFS1 n
REGISTER
DAC 4 n
REGISTER
OFFSET
DAC 1
DAC 4
BUFFER
GROUP 1
BUFFER
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
·
·
·
·
·
·
·
·
·
·DAC 7 n
REGISTER
DAC 7
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
SIGGND0
VREF1
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
Figure 1.
Rev. A
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