AD5360 Datasheet, PDF (1/25 Pages) Analog Devices – 16-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC

Preliminary Technical Data
16-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
AD5360/AD5361
FEATURES
16-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V digital interface
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical Line Cards
TEMP_OUT
PEC
MON_IN0
MON_IN1
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
FUNCTIONAL BLOCK DIAGRAM
DV_CC V_DD V_SS AGND DNGD
LDAC
TEMP
SENSOR
8
CONTROL
REGISTER
VOUT0 -
VOUT15
6
MUX
2
GPIO
REGISTER
SERIAL
INTERFACE
AD5360, n = 16
AD5361, n = 14
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
X1A REGISTER
n
MUX
n
n _{X1B REGISTER}
n
1
n
M REGISTER
n
C REGISTER
n
······
······
······ ······
n _{X1A REGISTER MUX n}
n
n _{X1B REGISTER}
n
1n
M REGISTER
n
C REGISTER
n
STATE
MACHINE
n
POWER-ON
RESET
AD5360/
AD5361
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
X1A REGISTER
n
MUX
n
n _{X1B REGISTER}
n
1
n
M REGISTER
n
C REGISTER
n
······
······
······ ······
n
X1A REGISTER
n
MUX
n
n _{X1B REGISTER}
n
1
n
M REGISTER
n
C REGISTER
n
14
OFS0 ¹⁴ OFFSET
REGISTER
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX ⁿ
2
·
·
·
·
·
·
MUX ⁿ
2
DAC 0 ⁿ
REGISTER
·
·
·
·
·
·
DAC 7 ⁿ
REGISTER
DAC 0
··
····
DAC 7
14
OFS1 ¹⁴ OFFSET
REGISTER
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX ⁿ
2
·
·
·
·
·
·
MUX ⁿ
2
DAC 0 ⁿ
REGISTER
·
·
·
·
·
·
DAC 7 ⁿ
REGISTER
DAC 0
··
····
DAC 7
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
···
·
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
GROUP 1
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·····
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5360-0001
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
Figure 1.
AD5360/AD5361—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
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