AD5347_15 Datasheet, PDF (1/24 Pages) Analog Devices – 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs

2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
FEATURES
GENERAL DESCRIPTION
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Readback
Buffered/unbuffered reference inputs
20 ns WR time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
The AD5346/AD5347/AD5348¹ are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
The GAIN pin on these devices allows the output range to be
set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
APPLICATIONS
An asynchronous CLR input is also provided, which resets the
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
Automatic test equipment
All three parts are pin compatible, which allows users to select
Mobile communications
the amount of resolution appropriate for their application
Programmable attenuators
Industrial process control
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
V_DD AGND DGND
V_REFAB
V_REFCD
BUF
GAIN
DB1... 1
DB0
CS
RD
WR
A2
A1
A0
CLR
LDAC
INTER-
FACE
LOGIC
AD5348
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
POWER-ON
RESET
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
V_OUTA
V_OUTB
V_OUTC
V_OUTD
V_OUTE
V_OUTF
V_OUTG
V_OUTH
POWER-DOWN
LOGIC
1_{Protected by U.S. Patent No. 5,969,657.}
V_REFGH
V_REFEF
PD
Figure 1.
Rev. 0
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