AD5259_15 Datasheet, PDF (1/24 Pages) Analog Devices – Nonvolatile, IC-Compatible 256-Position, Digital Potentiometer

Data Sheet
Nonvolatile, I²C-Compatible
256-Position, Digital Potentiometer
AD5259
FEATURES
Nonvolatile memory maintains wiper settings
256-position
Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm × 1.1mm) package
I²C®-compatible interface
V_LOGIC pin provides increased interface flexibility
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
Address Decode Pin AD0 and Pin AD1 allow
4 packages per bus
100-year typical data retention at 55°C
Wide operating temperature −40°C to +125°C
3 V to 5 V single supply
APPLICATIONS
LCD panel V_COM adjustment
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings
GENERAL DESCRIPTION
The AD5259 provides a compact, nonvolatile LFCSP-10
(3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function
as mechanical potentiometers¹ or variable resistors, but
with enhanced resolution and solid-state reliability.
The wiper settings are controllable through an I²C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
A separate V_LOGIC pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to four devices on the same bus.
FUNCTIONAL BLOCK DIAGRAMS
V_DD
V_LOGIC
GND
RDAC
EEPROM
RDAC
REGISTER
RDAC
A
W
B
SCL
SDA
AD0
AD1
I²C
SERIAL
INTERFACE
POWER-
ON RESET
8 DATA
8 CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL LOGIC
AD5259
V_LOGIC
Figure 1. Block Diagram
V_DD
A
EEPROM
SCL
SDA
AD0
AD1
I²C
SERIAL
INTERFACE
RDAC
REGISTER
AND
LEVEL
SHIFTER
W
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
Figure 2. Block Diagram Showing Level Shifters
CONNECTION DIAGRAM
W1
10 A
AD0 2 _AD5259 9 B
AD1 3 TOP VIEW 8 V_DD
SDA 4 ^{(Not to Scale)} 7 GND
SCL 5
6 V_LOGIC
Figure 3. Pinout
1 _{The terms digital potentiometer, VR (variable resistor), and RDAC are used}
interchangeably.
Rev. C
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