AD5025_15 Datasheet, PDF (1/28 Pages) Analog Devices – Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP

Fully Accurate, 12-/14-/16-Bit, Dual, V_OUT
nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
AD5025/AD5045/AD5065
FEATURES
Low power dual 12-/14-/16-bit DAC, ±1 LSB INL
Individual voltage reference pins
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V
3 power-down functions
Per channel power-down
Low glitch upon power-up
Hardware power-down lockout capability
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-lead TSSOP
APPLICATIONS
Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit
buffered voltage output nanoDAC® DACs offering relative accuracy
specifications of ±1 LSB INL with individual reference pins, and
can operate from a single 4.5 V to 5.5 V supply. The AD5025/
AD5045/AD5065 also offer a differential accuracy specification of
±1 LSB. The parts use a versatile 3-wire, low power Schmitt
trigger serial interface that operates at clock rates up to 50 MHz
and is compatible with standard SPI®, QSPI™, MICROWIRE™,
and DSP interface standards. The reference for the AD5025/
AD5045/AD5065 are supplied from an external pin and a refer-
ence buffer is provided on chip. The AD5025/AD5045/AD5065
incorporate a power-on reset circuit that ensures the DAC output
powers up zero scale or midscale and remains there until a valid
write takes place to the device. The AD5025/AD5045/AD5065
contain a power-down feature that reduces the current consump-
tion of the device to typically 400 nA at 5 V and provides software
selectable output loads while in power-down mode. The parts are
put into power-down mode over the serial interface. Total unad-
justed error for the parts is <2.5 mV. The parts exhibit very low
glitch on power-up. The outputs of all DACs can be updated
simultaneously using the LDAC function, with the added
functionality of user-selectable DAC channels to simultaneously
update. There is also an asynchronous CLR that clears all DACs
to a software-selectable code—0 V, midscale, or full scale. The
parts also feature a power-down lockout pin, PDL, which can be
used to prevent the DAC from entering power-down under any
circumstances over the serial interface.
PRODUCT HIGHLIGHTS
1. Dual channel available in a 14-lead TSSOP package with
individual voltage reference pins.
2. 12-/14-/16-bit accurate, ±1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
7. Power-down lockout capability.
Table 1. Related Devices
Part No.
Description
AD5666
Quad,16-bit buffered DAC, 16 LSB INL, TSSOP
AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
AD5062/AD5063
16-bit nanoDAC, 1 LSB INL, MSOP
AD5061
16-bit nanoDAC, 4 LSB INL, SOT-23
AD5040/AD5060
14-/16-bit nanoDAC, 1 LSB INL, SOT-23
FUNCTIONAL BLOCK DIAGRAM
POR
V_DD
V_REFA V_REFB
SCLK
SYNC
DIN
LDAC
SDO
LDAC
INPUT
REGISTER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC A
DAC B
PDL CLR
AD5025/AD5045/AD5065
Figure 1.
BUFFER
BUFFER
POWER-DOWN
LOGIC
GND
V_OUTA
V_OUTB
Rev. 0
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