AD5024 Datasheet, PDF (1/28 Pages) Analog Devices – Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP

Fully Accurate, 12-/14-/16-Bit V_OUT nanoDAC,
Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero-scale or midscale
3 power-down functions
Per-channel power-down
Low glitch on power-up
Hardware LDAC with LDAC override function
CLR function to programmable code
16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part No.
Description
AD5666
Quad,16-bit buffered DAC,16 LSB INL, TSSOP
AD5063/AD5062 16-bit nanoDAC, 1 LSB INL
AD5061
16-/14-bit nanoDAC, 4 LSB INL, SOT-23
AD5060/AD5040 16-/14-bit nanoDAC, 1 LSB INL, SOT-23
GENERAL DESCRIPTION
The AD5024/AD5044/AD5064 are low power, quad 12-/14-/
16-bit buffered voltage output nanoDAC® DACs that offer relative
accuracy specifications of 1 LSB INL with individual reference
pins and can operate from a single 4.5 V to 5.5 V supply. The
AD5024/AD5044/AD5064 parts also offer a differential accuracy
specification of ±1 LSB. The parts use a versatile 3-wire, low
power Schmitt trigger serial interface that operates at clock rates
up to 50 MHz and is compatible with standard SPI, QSPI™,
MICROWIRE™, and DSP interface standards. A reference buffer
is also provided on-chip. The AD5024/AD5044/AD5064 incor-
porate a power-on reset circuit that ensures the DAC output
powers up to zero scale or midscale and remains there until a
valid write takes place to the device. The AD5024/AD5044/
AD5064 contain a power-down feature that reduces the current
consumption of the device to typically 400 nA at 5 V and provides
software selectable output loads while in power-down mode.
Total unadjusted error for the parts is <2 mV.
PRODUCT HIGHLIGHTS
1. Quad channel available in 16-lead TSSOP package.
2. 16-bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Reset to known output voltage (zero scale or midscale).
AD5024/
AD5044/
AD5064 _LDAC
SCLK
SYNC
INTERFACE
LOGIC
DIN
LDAC CLR
FUNCTIONAL BLOCK DIAGRAM
V_DD
V_REFA V_REFB
INPUT
REGISTER
DAC
REGISTER
DAC A
INPUT
REGISTER
DAC
REGISTER
DAC B
INPUT
REGISTER
DAC
REGISTER
DAC C
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC D
POR
V_REFC V_REFD
Figure 1.
BUFFER
V_OUTA
BUFFER
V_OUTB
BUFFER
V_OUTC
BUFFER
POWER-DOWN
LOGIC
V_OUTD
GND
Rev. 0
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