AD4002 Datasheet, PDF (1/36 Pages) Analog Devices – Precision, Pseudo Differential, SAR ADCs

18-Bit, 2 MSPS/1 MSPS/500 kSPS,
Precision, Pseudo Differential, SAR ADCs
Preliminary Technical Data
AD4002/AD4006/AD4010
FEATURES
Throughput: 2 MSPS/1 MSPS/500 kSPS options
INL: ±2.0 LSB maximum
Guaranteed 18-bit, no missing codes
Low power
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
(VDD only)
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
SNR: 95 dB typical at 1 kHz, VREF = 5 V; TBD dB typical at 100 kHz
THD: −120 dB typical at 1 kHz, VREF = 5 V; TBD dB typical at
100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range
0 V to VREF with VREF from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay, valid first
conversion
First accurate conversion
Guaranteed operation: −40°C to +125°C
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
Ability to daisy-chain multiple ADCs and busy indicator
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
GENERAL DESCRIPTION
The AD4002/AD4006/AD4010 are low noise, low power, high
speed, 18-bit, precision successive approximation register (SAR)
analog-to-digital converters (ADCs). The AD4002, AD4006,
and AD4010 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
respectively. They incorporate ease of use features that reduce
signal chain power consumption, reduce signal chain
complexity, and enable higher channel density. The high-Z
mode, coupled with a long acquisition phase, eliminates the
need for a dedicated high power, high speed ADC driver, thus
broadening the range of low power precision amplifiers that can
drive these ADCs directly while still achieving optimum
performance. The input span compression feature enables the
ADC driver amplifier and the ADC to operate off common
supply rails without the need for a negative supply while
preserving the full ADC code range. The low serial peripheral
interface (SPI) clock rate requirement reduces the digital
input/output power consumption, broadens processor options,
and simplifies the task of sending data across digital isolation.
Operating from a 1.8 V supply, the AD4002/AD4006/AD4010
sample an analog input (IN+) from 0 V to VREF with respect to a
ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V. The
AD4002 consumes only 14 mW at 2 MSPS with a minimum SCK
rate of 75 MHz in turbo mode; the AD4006 consumes only
7 mW at 1 MSPS; and the AD4010 consumes only 3.5 mW at
500 kSPS. The AD4002/AD4006/AD4010 all achieve ±2.0 LSB
integral nonlinearity error (INL) maximum, no missing codes
at 18 bits, and 95 dB signal-to-noise ratio (SNR) for an input
frequency (fIN) of 1 kHz. The reference voltage is applied
externally and can be set independently of the supply voltage.
The SPI-compatible versatile serial interface features seven
different modes including the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus, and provides
an optional busy indicator. The AD4002/AD4006/AD4010 are
compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the
separate VIO supply.
The AD4002/AD4006 are available in a 10-lead MSOP and
10-lead LFCSP, and the AD4010 is available in a 10-lead LFCSP,
with operation specified from −40°C to +125°C. The devices are
pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8).
Rev. PrA
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