AD1878 Datasheet, PDF (1/16 Pages) Analog Devices – High Performance 16-/18-Bit Stereo ADCs

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High Performance
16-/18-Bit ⌺⌬ Stereo ADCs
AD1878/AD1879*
FEATURES
Fully Differential Dual Channel Analog Inputs
103 dB Signal-to-Noise (AD1879 typ)
–98 dB THD+N (AD1879 typ)
0.001 dB Passband Ripple and 115 dB Stopband
Attenuation
Fifth-Order, 64 Times Oversampling ⌺⌬ Modulator
Single Stage, Linear Phase Decimator
256 ؋ F_S Input Clock
APPLICATIONS
Digital Tape Recorders
Professional, DCC, and DAT
A/V Digital Amplifiers
CD-R
Sound Reinforcement
PRODUCT OVERVIEW
The AD1879 is a two-channel, 18-bit oversampling ADC based
on ∑∆ technology and intended primarily for digital audio appli-
cations. The AD1878 is identical to the 18-bit AD1879 except
that it outputs 16-bit data words. Statements in this data sheet
should be read as applying to both parts unless otherwise noted.
Each input channel of these ADCs is fully differential. Each
data conversion channel consists of a fifth order one-bit noise
shaping modulator and a digital decimation filter. An on-chip
voltage reference provides a voltage source to both channels sta-
ble over temperature and time. Digital output data from both
channels is time-multiplexed to a single, flexible serial interface.
The AD1878/AD1879 accepts a 256 × F_S input master clock.
Input signals are sampled at 64 × F_S on switched-capacitors,
eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With simpli-
fied antialiasing, linear phase can be preserved across the passband.
The AD1878/AD1879’s proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator’s quantization noise out of the audio passband. The
high order of the modulator randomizes the modulator output,
reducing idle tones in the AD1878/AD1879 to very low levels.
The AD1878/AD1879’s differential architecture provides in-
creased dynamic range and excellent common-mode rejection
characteristics. Because its modulator is single-bit, AD1878/
AD1879 is inherently monotonic and has no mechanism for
producing differential linearity errors.
The digital decimation filters are single-stage, 4095-tap finite
impulse response filters for filtering the modulator’s high fre-
quency quantization noise and reducing the 64 × F_S single-bit
output data rate to a F_S word rate. They provide linear
*Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.
FUNCTIONAL BLOCK DIAGRAM
LRCK 1
BCK 2
S0 3
64/32 4
DV_DD 5
DGND 6
NC 7
AV_SS1 8
AV_SS2 9
AGND 10
APD 11
VINR– 12
VINR+ 13
REFR 14
SERIAL OUTPUT
INTERFACE
DIGITAL
CHIP
SINGLE-STAGE,
4k-TAP
FIR DECIMATION
FILTER
SINGLE-STAGE,
4k-TAP
FIR DECIMATION
FILTER
ANALOG
D
D CHIP D
D
A
A
A
A
C
C
C
C
VOLTAGE
REFERENCE
28 WCK
27 DATA
26 CLOCK
25 S1
24 _RESET
23 DGND
22 DV_DD
21 AV_SS1
20 _AVDD2
19 AV_DD1
18 AGND
17 VINL–
16 VINL+
15 REFL
phase and a narrow transition band that permits the digitization
of 20 kHz signals while preventing aliasing into the passband
even when using a 44.1 kHz sampling frequency. Passband
ripple is less the 0.001 dB, and stopband attenuation exceeds
115 dB.
The flexible serial output port produces data in twos-complement,
MSB-first format. Input and output signals are to TTL and
CMOS-compatible logic levels. The port is configured by pin
selections. The AD1878/AD1879 can operate in either master
or slave mode. Each 16-/18-bit output word of a stereo pair can
be formatted within a 32-bit field as either right-justified, I²S-
compatible, or at user-selected positions. The output can also be
truncated to 16-bits by formatting into a 16-bit field.
The AD1878/AD1879 consists of two integrated circuits in a
single ceramic 28-pin DIP package. The modulators and refer-
ence are fabricated in a BiCMOS process; the decimator and
output port, in a 1.0 µm CMOS process. Separating these func-
tions reduces digital crosstalk to the analog circuitry. Analog and
digital supply connections are separated to further isolate the
analog circuitry from the digital supplies.
The AD1878/AD1879 operates from ± 5 V power supplies over
the temperature range of –25°C to +70°C.
REV. 0
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which may result from its use. No license is granted by implication or
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