AD1845_15 Datasheet, PDF (1/40 Pages) Analog Devices – Parallel-Port 16-Bit SoundPort Stereo Codec

a
Parallel-Port 16-Bit
SoundPort^® Stereo Codec
AD1845
FEATURES
plete on-chip filtering, MPC Level-2 compliant analog mixing,
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Microsoft^® and Windows^® Sound System Compatible
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
MPC Level-2+ Compliant Mixing
down modes. It provides a direct, byte-wide interface to both
16 mA Bus Drive Capability
ISA (“AT”) and EISA computer buses for simplified implemen-
Supports Two DMA Channels for Full Duplex Operation tation on a computer motherboard or add-in card.
On-Chip Capture and Playback FIFOs
The AD1845 SoundPort Stereo Codec supports a DMA re-
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
E _{Byte-Wide Parallel Interface to ISA and EISA Buses}
Pin Compatible with AD1848, AD1846, CS4248, CS4231
T _{PRODUCT OVERVIEW}
The Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
E _{integrated circuit. The AD1845 provides a complete, single chip}
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
(Continued on Page 9)
L _{FUNCTIONAL BLOCK DIAGRAM}
ANALOG
ANALOG SUPPLY
DIGITAL SUPPLY
CLOCK SOURCE POWER DOWN
RESET
DIGITAL
O ^L_MIC
R_MIC
L_LINE
R_LINE
L_AUX1
S _{R_AUX1}
B _{L_OUT}
M_OUT
O _{R_OUT}
0 dB/
20 dB
VARIABLE SAMPLE
FREQUENCY GENERATOR
AD1845
GAM
GAM
L
M
GAIN
U
⌺⌬ A/D
CONVERTER
␮-LAW
XR
GAIN
⌺⌬ A/D
CONVERTER
A-LAW
FIFO
LINEAR
P
A
R
A
L
GAM GAM = GAIN
DIGITAL MIX
L
ATTENTUATE
ATTENUATE
E
MUTE
L
⌺
⌺
⌺
L _ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
⌺
␮-LAW
P
O
MUTE ⌺
⌺
⌺
R
⌺
ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
A-LAW
FIFO
R
LINEAR
T
⌺
PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ
CAPTURE ACK
ADR1:0
DATA7:0
CS
RD
WR
BUS DRIVER
CONTROL
HOST DMA
INTERRUPT
M_IN
GAM
GAM
EXTERNAL
CONTROL
L_AUX2
R_AUX2
REFERENCE
CONTROL
REGISTERS
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
V_{REF_F} V_REF
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
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© Analog Devices, Inc., 1997