AD15252_15 Datasheet, PDF (1/20 Pages) Analog Devices – 12-Bit, 65 MSPS, Dual ADC

12-Bit, 65 MSPS, Dual ADC
AD15252
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-bit, 65 MSPS dual ADC
Differential input with 100 Ω input impedance
Full-scale analog input: 296 mV p-p
170 MHz, 3 dB bandwidth
OTR_A
PDWNA
CLKA
AD15252
OBSOLETE SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN)
SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN)
435 mW per channel
Dual parallel output buses
Out-of-range indicators
Independent clocks
Duty cycle stabilizer
Twos complement or offset binary data format
APPLICATIONS
Antijam GPS receivers
Wireless and wired broadband communications
Communications test equipment
INA
OEB_A
DFS
PDWNB
CLKB
INB
OEB_B
OTR_B
LPF
LPF
Figure 1.
DATA
BUS A
DATA
BUS B
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital
converter (ADC). It features a differential front-end
amplification circuit followed by a sample-and-hold amplifier
and multistage pipeline ADC. It is designed to operate with a
3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input
is fully differential, ac-coupled, and terminated in 100 Ω input
impedances. The full-scale differential signal input range is
296 mV p-p.
Two parallel, 12-bit digital output buses provide data flow from
the ADCs. The digital output data is presented in either straight
binary or twos complement format. Out-of-range (OTR) signals
indicate an overflow condition, which can be used with the
most significant bit to determine low or high overflow. Dual
single-ended clock inputs control all internal conversion cycles.
A duty cycle stabilizer allows wide variations in the clock duty
cycle while maintaining excellent performance. The AD15252 is
optimized for applications in antijam global positioning
receivers and is well suited for communications applications.
1. Dual 12-bit, 65 MSPS ADC with integrated analog signal
conditioning optimized for antijam global positioning
system receiver (AJ-GPS) applications.
2. Operates from a single 3.3 V power supply and features a
separate digital output driver supply to accommodate 2.5 V
and 3.3 V logic families.
3. Packaged in a space-saving 8 mm × 8 mm chip scale
package ball grid array (CSP_BGA) and is specified over
the industrial temperature range (–40°C to +85°C).
Rev. 0
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