PAC5255 Datasheet, PDF (43/71 Pages) Active-Semi, Inc – Power Application Controller

PAC5255
Power Application Controller
12.3.6. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using two protection event signals from the
Configurable Analog Front End (CAFE), designated as protection event 1 (PR1) and protection event 2 (PR2) signals. The
DRL0/DRL1/DRL2 drivers are designated as low-side group 1, and the DRL3/DRL4/DRL5 gate drivers are designed as
low-side group 2. The DXH0/DXH1/DXH2 ultra-high-voltage gate drivers are designated as high-side group 1. The PR1
signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit
settings. The PR2 signal from the CAFE can be used to disable low-side group 2, high-side group 2, or both depending on
the PR2 mask bit settings. ENHS2 (high-side group 2 control output) pin is provided for enabling external power drivers
with fault protection.
12.3.7. Low-Speed Clock Output
The ASPD incorporates an option for a low-speed clock output. This is primarily for applications which need to measure an
internally generated clock, to compare it to the main clock (such as IEC 60730 Class B Safety). By default, the
CLKOUT/ENHS2 pin will generate a 290Hz 5V square wave clock, but this pin can be configured to change the clock
frequency (290Hz, 580Hz or 1.16kHz), or select between output clock and ENHS2 (high-side group 2 control output – as
described above).
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Rev 1.1‒April 15, 2016