A54SX72A-CQ256 Datasheet, PDF (65/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
Table 2-36 • A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions V_CCA = 2.25 V, V_CCI = 2.25 V, T_J = 70°C)
–3 Speed* –2 Speed –1 Speed
Std. Speed
–F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_QCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
3.0
3.4
3.9
4.6
6.4 ns
t_QCHKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.9
3.4
3.8
4.5
6.3 ns
t_QPWH
Minimum Pulse Width High
1.5
1.7
2.0
2.3
3.2
ns
t_QPWL
Minimum Pulse Width Low
1.5
1.7
2.0
2.3
3.2
ns
t_QCKSW
Maximum Skew (Light Load)
0.2
0.3
0.3
0.3
0.5 ns
t_QCKSW
Maximum Skew (50% Load)
0.4
0.5
0.5
0.6
0.9 ns
t_QCKSW
Maximum Skew (100% Load)
0.4
0.5
0.5
0.6
0.9 ns
Note: *All –3 speed grades have been discontinued.
v5.3
2-45