APA075-PQG208 Datasheet, PDF (59/178 Pages) Actel Corporation – ProASIC Flash Family FPGAs

Table 2-41 • Worst-Case Military Conditions
V_DDP = 3.0V, V_DD = 2.3V, T_J = 125°C for Military/MIL-STD-883
Macro Type
GL33
GL33S
Description
3.3V, CMOS Input Levels³, No Pull-up Resistor
3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger
PECL
PPECL Input Levels
Notes:
1. t_INYH = Input Pad-to-Y High
2. t_INYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, V_DDP = 2.3 V for delays.
Table 2-42 • Worst-Case Military Conditions
V_DDP = 2.3V, V_DD = 2.3V, T_J = 125°C for Military/MIL-STD-883
Macro Type
GL25LP
GL25LPS
Description
2.5V, CMOS Input Levels³, Low Power
2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger
Notes:
1. t_INYH = Input Pad-to-Y High
2. t_INYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, V_DDP = 2.3 V for delays.
ProASIC^PLUS Flash Family FPGAs
Max. t_INYH1
Std.
1.1
1.1
1.1
Max. t_INYL2
Std.
1.1
1.1
1.1
Max. t_INYH1
Std.
1.0
1.4
Max. t_INYL2
Std.
1.1
1.0
v5.9
2-49