A54SX16A-TQ100 Datasheet, PDF (34/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
SX-A Timing Model
Input Delays
I/O Module
t_INYH= 0.6 ns
t_RD1 = 0.3 ns
t_RD2 = 0.5 ns
Internal Delays
Combinatorial
Cell
Predicted
Routing
Delays
Output Delays
I/O Module
t_PD = 1.1 ns
Register
Cell
ttt_RRRDDD841
=
=
=
0.3
0.9
1.5
ns
ns
ns
t_DHL = 3.9 ns
I/O Module
t_DHL = 3.9 ns
D
t
t
SUD ^{= 0.8 ns}
HD ^{= 0.0 ns}
Q
t_RD1 = 0.3 ns
Routed
Clock
t_RCKH = 3.0 ns
(100% Load)
t_RCO= 0.8 ns
I/O Module
t_INYH= 0.6 ns
Register
Cell
DQ
t_SUD = 0.8 ns
t_RD1 = 0.3 ns
t_HD = 0.0 ns
Hardwired
Clock
t_HCKH= 1.8 ns
t_RCO= 0.8 ns
t_ENZL= 1.5 ns
I/O Module
t_DHL = 3.9 ns
t_ENZL= 1.5 ns
Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.
Figure 2-3 • SX-A Timing Model
Sample Path Calculations
Hardwired Clock
External Setup
= (t_INYH + t_RD1 + t_SUD) – t_HCKH
= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns
Clock-to-Out (Pad-to-Pad) = t_HCKH + t_RCO + t_RD1 + t_DHL
= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns
Routed Clock
External Setup
= (t_INYH + t_RD1 + t_SUD) – t_RCKH
= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns
Clock-to-Out (Pad-to-Pad) = t_RCKH + t_RCO + t_RD1 + t_DHL
= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns
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v5.3